The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

A turbo encoding method includes obtaining a code block for turbo encoding, storing a data block of the code block in a plurality of parallel caches, and obtaining parallel data from the plurality of parallel caches for turbo encoding.

An encoder encodes input data utilizing a binary symmetry-invariant product code including D data bits and P parity bits in each dimension. The encoder includes a half-size data array including K subarrays each having multiple rows of storage for H bits of data, where D is an integer equal to 2H+1 and K is an integer that is 2 or greater. The encoder is configured to access K rows of data by reading a respective H-bit data word of input data from each of the multiple subarrays and K H-bit data words of duplicate data from across multiple different rows of the subarrays. The encoder further includes at least one register configured to receive the bits read from the half-size data array code and rotate them as needed, at least one row parity generator, and a column parity generator that generates column parities based on row parity.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A new unequal-error-protection method that is based on using a particular parity-check-matrix structure for LDPC codes.

A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

This application provides a channel encoding method, an encoding apparatus, and a system. A bit sequence X.sub.1.sup.N is output by using X.sub.1.sup.N=D.sub.1.sup.N F.sub.N, where D.sub.1.sup.N is a bit sequence obtained after an input bit sequence u.sub.1.sup.N is encoded based on locations of K to-be-encoded information bits in an encoding diagram that has a mother code length of N, u.sub.1.sup.N is a bit sequence obtained based on the K to-be-encoded information bits, and F.sub.N is a Kronecker product of log.sub.2 N matrices F.sub.2. In the foregoing technical solution, in particular, a design considers that the locations of the K to-be-encoded information bits in the encoding diagram that has a mother code length of N include a row location index set H of the information bits in the encoding diagram and a layer location index set M of the information bits in the encoding diagram, where 0HN, and 0<Mlog.sub.m N1.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.