This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.

An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a k-bit original data in parallel and configured to perform a plurality of XOR operations to the k-bit original data to output a (nk)-bit parity data. The k-bit original data and the (nk)-bit parity data form an n-bit codeword, k denotes a natural number and n denotes a natural number which is greater than k.

For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.

For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Methods of transmitting blocks of incremental redundant coded bits are provided. Methods include concatenating, using an outer encoder, bits of an input bit vector to an outer encoded bit vector that has fewer bits than the input bit vector, wherein the outer encoded bit vector includes a mixture of information bits from the input bit vector. Methods include encoding the outer encoded bit vector into inner encoded data that is mapped to multiple data transmission channels that each include a channel reliability value. A first portion of the data transmission channels is used to transmit information bits corresponding to the outer encoded bit vector and a second portion of the data transmission channels is used to transmit frozen bits that include no information.

Systems and techniques described herein include jointly decoding coded data of different codes, including different coding algorithms, finite fields, and/or source blocks sizes. The techniques described herein can be used to improve existing distributed storage systems by allowing gradual data migration. The techniques can further be used within existing storage clients to allow application data to be stored within diverse different distributed storage systems.

Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.