Methods and apparatus for preference based selection of storage network memory for data storage. In an example, a computing device receives a data object for storage in memory of the storage network and determines a system level storage efficiency preference associated with the data object. The computing device selects a set of storage nodes of a plurality of sets of storage nodes for storage of the data object based, at least in part, on the system level storage efficiency preference. The computing device further determines dispersed storage error encoding parameters for the data object, encodes the data object in accordance with the dispersed storage error encoding parameters to produce encoded data slices, and generates system addressing information for the encoded data slices.

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n, thereby to define a codeword, having n.sup.2 code symbols corresponding to respective locations of the array, of a quarter product code defined by C.sub.Q={XX.sup.T(XX.sup.T).sup.F: XC} where X is an n by n-symbol matrix defining a codeword of the product code, X.sup.T is the transpose matrix of X, and (XX.sup.T).sup.F is a reflection of matrix (XX.sup.T) in the anti-diagonal thereof.

A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n, thereby to define a codeword, having n.sup.2 code symbols corresponding to respective locations of the array, of a quarter product code defined by C.sub.Q={XX.sup.T(XX.sup.T).sup.F: XC} where X is an n by n-symbol matrix defining a codeword of the product code, X.sup.T is the transpose matrix of X, and (XX.sup.T).sup.F is a reflection of matrix (XX.sup.T) in the anti-diagonal thereof.

An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a k-bit original data in parallel and configured to perform a plurality of XOR operations to the k-bit original data to output a (nk)-bit parity data. The k-bit original data and the (nk)-bit parity data form an n-bit codeword, k denotes a natural number and n denotes a natural number which is greater than k.

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits and a target constraints vector, placing the information bits in an input vector, setting balance bits included in the input vector to zero, encoding the input vector using a systematic code to obtain a preliminary codeword, applying a constraints matrix to the preliminary codeword to obtain a preliminary constraints vector, applying a transition matrix to a sum of the preliminary constraints vector and the target constraints vector to determine updated balance bits, obtaining an output codeword based on the information bits and the updated balance bits, and storing the output codeword in the storage device.

Systems and methods are disclosed for decoding wireless signals. For example, a wireless device may receive a wireless signal, de-interleave the received wireless signal to produce a first encoded signal and a second encoded signal, generate a first set of a priori log likelihood ratios (LLRs) by decoding and de-interleaving the first encoded signal, and recover a set of information bits from the received wireless signal based at least in part on the second encoded signal and the first set of a priori LLRs.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.