A channel encoding method and apparatus. The method includes: obtaining A to-be-encoded information bits; mapping the A to-be-encoded information bits and L CRC bits to a first bit sequence based on an interleaving sequence, where the L CRC bits are obtained based on the A to-be-encoded information bits and a CRC polynomial, the interleaving sequence is obtained from a prestored interleaving sequence table or is obtained based on a maximum-length interleaving sequence, A+L is less than or equal to Kmax, and Kmax is a length of the maximum-length interleaving sequence; and encoding the first bit sequence. In this way, not only an encoding delay can be reduced, but also decoding has an early stop capability, so that decoding can end in advance, thereby reducing a decoding delay.

Methods, systems, and devices for wireless communication are described for dynamic frozen bits of polar codes for early termination and performance improvement. A wireless device may receive a signal comprising a codeword encoded using a polar code. The wireless device may perform decoding of the codeword including at least: parity check of a first subset of decoding paths for making a decision on early termination of decoding of the codeword based on dynamic frozen bits, and generating path metrics for a second subset of the decoding paths that each pass the parity check based on the dynamic frozen bits, and performing error detection on a bit sequence corresponding to one of the second subset of the decoding paths based at part on error detection bits and the generated path metrics. The wireless device may process the information bits based on a result of the decoding.

According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

A method and an apparatus for encoding a polar code concatenated with a cyclic redundancy check (CRC), where M bits are selected from K bits in the sequence to perform CRC encoding. The M bits are determined based on reliability of K polarized subchannels on which the K bits are placed and/or row weights of K rows, in a first matrix, corresponding to the K polarized subchannels on which the K bits are placed. The first matrix is an encoding matrix of polar encoding. Polar encoding is performed on the K bits and obtained CRC check bits. An encoded codeword is output.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

Apparatuses for transmitting and receiving a signal in a communication system are provided. An apparatus of a receive device includes a receiver configured to receive, from a transmit device, a signal comprising remaining bits of parity bits after puncturing, wherein the parity bits are obtained by adding at least one shortened bit to information bits to obtain input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding; and a hardware processor configured to determine a number of puncture bits for the parity bits, generate an output signal by adding at least one value corresponding to the number of the puncture bits to the signal, and decode the output signal.

A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.