Techniques described and suggested herein include systems and methods for optimizing random access characteristics for data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be configured such that a variable number of the shards can be leveraged to meet random access requirements for retrieval requests associated with the archives stored and/or encoded therein. Implementing systems may monitor random access rates, capabilities, and burdens, so as to adaptively account for changes to some or all of the monitored parameters.

Systems and methods are disclosed for providing H-ARQ transmissions in respect of a set of horizontal code blocks are combined in a code. Retransmissions contain vertical parity check blocks which are determined from verticals from the set of horizontal code blocks. Once all the vertical parity check blocks have been transmitted, a new set may be determined after performing interleaving upon either the content of the horizontal code blocks, in the case of non-systematic horizontal code blocks, or over the content of encoder input bits in the place of systematic horizontal code blocks. The interleaving may be bitwise or bit subset-wise. The retransmissions do not contain any of the original bits. In the decoder, soft decisions are produced, and nothing needs to be discarded; decoding will typically improve with each retransmission.

The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.

A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.

A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

A method includes generating a first error correcting code (ECC) codeword and a second ECC codeword. The method further includes generating redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword. The method further includes storing the first ECC codeword, the second ECC codeword, and the redundancy information at a word line of a memory of a data storage device.

A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.

The current invention relates to an encoder for converting a set of data words into a data block having a header section, a checksum section and a payload section; the encoder comprising: a header inserter arranged to insert a header pattern in the data block; a checksum calculator arranged to calculate a checksum of the set of data words; a data word converter arranged to convert the set of data words into a set of obfuscated data words being a result of applying an exclusive or operation between the set of data words and the checksum.

An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.