Embodiments of the present disclosure disclose a communication method and apparatus, including: obtaining to-be-encoded first information, where the first information includes a first information bit set and a second information bit set, bits included in the first information bit set are able to be obtained through correct decoding by a plurality of terminal devices, and bits included in the second information bit set are able to be obtained through correct decoding by some of the plurality of terminal devices; performing first polar encoding on the first information bit set to obtain first encoded information; performing second polar encoding on the second information bit set based on the first encoded information to obtain second encoded information; and outputting the second encoded information. Resources can be saved by implementing the embodiments of the present disclosure.

A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.

Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.

Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.

A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.

In certain aspects, a method for sending data over a bus comprises: calculating a parity check code for a new data code, wherein the new data code comprises a number of bits in the new data code; calculating a Hamming distance between the new data code and a prior data code; and if the Hamming distance is greater than half of the number of bits in the new data code: inverting the new data code and the parity check code to obtain an inverted new data code and an inverted parity check code; and sending the inverted new data code and the inverted parity check code to the bus.

A method performed at an electronic device comprises receiving information bits, a first nub, and a second nub, each nub comprising redundant values; calculating first calculated determiners from first subsets of the information bits along a first dimension; calculating first corrected determiners by applying first FEC decoding to a combination of the first calculated determiners and the first nub; correcting at least one error in the information bits using a difference between the first corrected determiners and the first calculated determiners; calculating second calculated determiners from second subsets of the information bits along a second dimension that differs from the first dimension; calculating second corrected determiners by applying second FEC decoding to a combination of the second calculated determiners and the second nub; and correcting at least one additional error in the information bits using a difference between the second corrected determiners and the second calculated determiners.

In certain aspects, a method for sending data over a bus comprises: calculating a parity check code for a new data code, wherein the new data code comprises a number of bits in the new data code; calculating a Hamming distance between the new data code and a prior data code; and if the Hamming distance is greater than half of the number of bits in the new data code: inverting the new data code and the parity check code to obtain an inverted new data code and an inverted parity check code; and sending the inverted new data code and the inverted parity check code to the bus.

A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor. The storage unit stores the binary query vector and the plurality of candidate vectors, and the processor performs Tanimoto calculations in terms of Hamming distances. The processor includes a Tanimoto to Hamming threshold converter, a Hamming measurer, and a Hamming comparator. The Tanimoto to Hamming threshold converter converts a Tanimoto threshold into a Hamming threshold. The Hamming measurer measures the Hamming distances between the candidate vectors and the query vector. The Hamming comparator selects candidate vectors whose Hamming distance from the query vector is less than or equal to the Hamming threshold.

A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A−10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.