Methods, apparatus, systems, architectures and interfaces for encoding/decoding a QD-DTS-PrCC are provided. The decoding method includes determining a number k.sub.TS of input bits included in a transmission of a data stream and a first bit of the input bits included in the transmission in the data stream; determining a number of Encoded Bit Blocks (EBBs), each of the EBBs including any number of data blocks that are previously transmitted Transmit Segments (TS) of the data stream, each of the data blocks having a bit length of k.sub.TS bits; selecting that number of EBBs for encoding a QD-DTS-PrCC component codeword (QDCC) of the transmission according to a DTS indexing method for indexing a plurality of EBBs; generating the QDCC including a TS, Virtual Segments (VSs), and r.sub.c parity bits, a dimensionality of the QD-DTS-PrCC being at least 2; and extracting the calculated TS of the QDCC to an output EBB.

In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.

Various embodiments are directed to Reed-Muller decoding systems and methods based on recursive projections and aggregations of cosets decoding, exploiting the self-similarity of RM codes, and extended with list-decoding procedures and with outer-code concatenations. Various embodiments are configured for decoding RM codes (and variants thereof) over binary input memoryless channels, such as by, for each received word of RM encoded data, projecting the received word onto each of a plurality of cosets of different subspaces to form thereby a respective plurality of projected words; recursively decoding each of the respective plurality of projected words to form a respective plurality of decoded projected words; and aggregating each of the respective decoded projected words to obtain thereby a decoding of the corresponding received word of RM encoded data.

The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.