A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

A memory system includes a memory device including a plurality of memory blocks and a controller suitable for selecting first memory blocks, the number of valid pages of which is equal to or less than a first threshold value, among the plurality of memory blocks, and performing a garbage collection operation on the first memory blocks based on error bit information of the first memory blocks.

Disclosed is a method for processing code blocks as implemented by a baseband processor. The method involves performing a cyclic redundancy check on decoded and deinterleaved code blocks until one fails its CRC check. On first failure the baseband processor requests a retransmission of the code blocks and resumes CRC checks on the retransmitted code blocks, beginning at the code block that had failed. In the event of subsequent failures, the baseband processor performs a soft combine on the failed retransmitted block with its original transmitted counterpart. Only if the soft combined code block fails does the baseband processor request another retransmission. In this case, subsequent CRC failures result in soft combines of three corresponding code words, making the process more robust. The method reduces the number of retransmissions as well as the computing resources needed for processing incoming code blocks.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

The present invention discloses a method for fusing baseband resources between networks of different standards. The method includes the following steps: performing coding on baseband data by using a coding scheme of a first network, and then performing modulation by using a modulation scheme of a second network. The present invention further discloses a corresponding base station and a terminal. In the present invention, in a case of collocation/co-device or a co-baseband resource pool, a correspondence between channel coding/de-coding and modulation/demodulation in each network is changed to enable the network to implement dynamic matching according to a specific factor such as a network status service type, thereby improving system performance of the network and significantly improving transmission performance.

A decoding module for a communication device includes a first calculation circuit, outputting the larger between a first parameter and a second parameter as a first output parameter; a first arithmetic circuit, calculating a first product of a third parameter and a first slope, and a first difference between a first constant and the first product; a second arithmetic circuit, calculating a second product of the third parameter and a second slope, and a second difference between a second constant and the second product; a second calculation circuit, selecting the largest among a third constant, the first difference and the second difference and generating a second output parameter, wherein the third constant is zero; and an addition circuit, adding the first output parameter and the second output parameter to generate output information, according to which the communication device determines a data bit.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

A turbo equalization device includes equalization circuitry, which in operation, performs an equalization process M times on an input signal, M being an integer equal to or more than 1; counter circuitry, which in operation, counts an iteration number m that indicates a number of the performed equalization process, m being an integer equal to or more than 0 and equal to less than M; control circuitry, which in operation, determines an iteration number N of a decoding process for the m times equalization processed input signal according to the iteration number m of the equalization process, the decoding process using an error correcting code that uses a belief propagation algorithm, N being an integer equal to or more than 1; and decoding circuitry, which in operation, performs a decoding process N or less times on the m times equalization processed input signal.