An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition.

Methods and apparatus disclosed herein may be used to establish framing more efficiently in communication protocols with block-coded forward error correction. Such protocols generally involve the check of different bit-alignments searching for positions that yield zero syndromes. The search can be undesirably slow, particularly in the presence of received errors. The presently-disclosed bit-alignment testing technique reduces this search time by checking the syndrome at each data word as if that data word was the last of a code. In other words, the word positions are effectively checked without a prior assumption as to which words are the first and last of the code. This reduces the task to the number of different bit-alignments possible within a single data word, rather than the number of bit-alignments possible in a complete FEC code. In one implementation, the lock time is reduced by approximately 50 times when compared to a straightforward solution.

A method and apparatus are provided for performing consistency testing for a Bose-Chaudhuri-Hocquenghem (BCH) error corrected first sub-frame of navigation message broadcast from a satellite of a GNSS. Consistency testing is performed by comparing BCH encoded portion(s)s of data symbols with elements of look up table(s) to see if such portions are similar to element(s) of the look up table(s).

The present disclosure relates to information processing methods and apparatus, communications devices, and communications systems. One example method includes adding redundancy check bits to a bit sequence A to obtain a bit sequence C, performing cyclic shift on the bit sequence C based on a shift t and a lifting factor z to obtain a bit sequence C.sup.t, where t is an integer greater than or equal to 0, and the shift t is obtained based on second information, and performing low-density parity-check (LDPC) encoding on the bit sequence C.sup.t to obtain a bit sequence D.sup.t.

The current invention relates to an encoder for converting a set of data words into a data block having a header section, a checksum section and a payload section; the encoder comprising: a header inserter arranged to insert a header pattern in the data block; a checksum calculator arranged to calculate a checksum of the set of data words; a data word converter arranged to convert the set of data words into a set of obfuscated data words being a result of applying an exclusive or operation between the set of data words and the checksum.

The present invention discloses a coding and decoding method, apparatus, and system for forward error correction, and pertains to the field of communications. The method includes: determining check matrix parameters of time-varying periodic LDPC convolutional code according to performance a transmission system, complexity of the transmission system, and a synchronization manner for code word alignment, constructing a QC-LDPC check matrix according to the determined check matrix parameters, and obtaining a check matrix (H.sub.c) of the time-varying periodic LDPC convolutional code according to the QC-LDPC check matrix; de-blocking, according to requirements of the H.sub.c, data to be coded, and coding data of each sub-block according to the H.sub.c, so as to obtain multiple code words of the LDPC convolutional code; and adding the multiple code words of the LDPC convolutional code in a data frame and sending the data frame.

Embodiments provide a transfer method for wirelessly transferring data in a communication system (e.g. a sensor network or telemetry system). The data includes core data and extension data, wherein the core data is encoded and distributed in an interleaved manner to a plurality of core sub-data packets, wherein the extension data is encoded and distributed in an interleaved manner to a plurality of extension sub-data packets, wherein at least a part of the core data contained in the core sub-data packets is needed for receiving the extension data or extension data packets.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive a data packet that includes at least in part a preamble, an encoded block, and a payload. The apparatus may detect the preamble of the data packet at a last symbol of the preamble or prior to the last symbol of the preamble. The apparatus may compute a branch metric for each of a plurality of transitions between states. The apparatus may initialize a path metric for each of a plurality of non-synchronization states and synchronization states. In certain aspects, each of the synchronization states may be associated with the preamble. The apparatus may determine a survivor path for each of the non-synchronization states and synchronization states based at least in part on a respective path metric. The apparatus may determine a traceback timing.