Methods, systems, and devices for wireless communication are described that support communication of information buts based on reference signal index modulation (RS-IM). A base station and a UE may transmit a number of downlink and uplink information bits (e.g., downlink control bits, uplink control bits) using index modulation schemes applied on references signals. A base station and a UE may transmit reference signal transmissions using reference signal index modulation, in which a set of information bits may be encoded using one or more coding techniques, in conjunction with RS-IM techniques, to enhance reliability of some or all of the information bits. Error detection bits may be added to the information bits, and included when coding is performed. Coding may include channel coding, repetition of reference signals for combining at a receiving device, or any combinations thereof.

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

The present invention relates to data transmission/reception methods using a polar coding scheme, and devices for supporting same. The method for transmitting data by using polar coding in a wireless access system, according to one embodiment of the present invention, may comprise the steps of deriving Bhattacharyya parameters according to data bits input for finding noise-free channels among equivalent channels; allocating data payloads comprising data bits and cyclic redundancy check (CRC) bits to the found noise-free channels; inputting the data payloads into a polar encoder; and transmitting code bits output by the polar encoder, wherein the CRC bits may be allocated to better noise-free channels, among the noise-free channels indicated by the Bhattacharyya parameters, than the data bits.

According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.

Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

Apparatuses, methods and storage medium associated with generating erasure codes for data to be stored in a storage system. In embodiments, a method may include launching, by storage system, a plurality of instances of an erasure code generation module, based at least in part on hardware configuration of the storage system. Additionally, the method may further include setting, by the storage system, operational parameters of the plurality of instances of the erasure code generation module, based at least in part on current system load of the storage system. Further, the method may include operating, by the storage system, the plurality of instances of the erasure code generation module to generate erasure codes for data to be stored in the storage system, in accordance with the operational parameters set. Other embodiments may be described and claimed.

A signal processing device includes a distributing unit and a plurality of correcting units with different processing performance, the distributing unit distributes a bit sequence having a first number of bits to the first correcting unit, and a bit sequence having a second number of bits less than the first number of bits to the second correcting unit having lower processing performance than the first correcting unit, the first correcting unit applies error correction processing to the bit sequence having the first number of bits distributed to the first correcting unit, and the second correcting unit applies error correction processing to the bit sequence having the second number of bits distributed to the second correcting unit.

A controller has an error correction capability by including: a state monitoring unit that analyzes a state of a monitoring target and outputs state information; an error correction processing unit that switches error correction codes so that a correction rate for the respective states becomes a value within a predetermined range; and a correction rate calculation unit that calculates the correction rate for the respective states based on the correction result by the error correction processing unit.

A system and method is disclosed for fast parallel data processing in a distributed storage system. An example method includes receiving at least one digital object; determining, by a processor of a computing device, whether the at least one digital object has a fixed data block structure; in response to determining that the at least one digital object has a fixed data block structure, determining by the processor a size of each fixed data block of the at least one digital object; determining a number of archive chunks for storing the at least one digital object on a selected plurality of storage servers based at least upon the size of each fixed data block; and partitioning the at least one digital object into the number of archive chunks for storing on the selected plurality of storage servers using erasure coding.

A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.