Patent classifications
H03M13/356
PROCESSING PROBLEMATIC SIGNAL MODULATION PATTERNS AS ERASURES USING WIRELESS COMMUNICATION DEVICES
Methods and apparatus are provided for controlling wireless signal transmissions, wherein problematic symbol patterns are relocated to an erasure region of a data packet prior to erasure encoding and transmission. Relocating the problematic symbol patterns is done so that, when the resulting erasure codeword is punctured and transmitted, the problematic patterns are not transmitted. Yet, those patterns can be restored by the decoder at the receiving device using an erasure decoder in accordance with erasure decoding techniques, e.g., punctured low-density parity-check (LDPC) decoding techniques. In this manner, problematic symbol patterns that may be corrupting during transmission due to noise are removed (punctured) prior to transmission, then restored by the decoder during decoding.
Communications Method, Apparatus, and System
This application discloses a communications method, apparatus, and system, and is applicable to wireless communication fields such as the internet of vehicles, intelligent driving, assisted driving, and intelligent connected vehicles. The communications method may include: encoding first data according to a first coding scheme; sending the encoded first data; encoding second data according to a second coding scheme, where the first data is different from the second data, and the second coding scheme is different from the first coding scheme; and sending the encoded second data.
Transmitter and method for transmitting data block in wireless communication system
Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (N.sub.ES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the N.sub.ES and generating a coded block; parsing the coded block based on the s and the N.sub.ES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.
Transmitter apparatus and signal processing method thereof
A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.
TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF
A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.
ERROR COALESCING
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
Multi-level channel coding for wireless communications
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may segment a plurality of bits of a communication into a first set of bits and a second set of bits; process the first set of bits using a first processing chain and the second set of bits using a second processing chain, wherein the first set of bits is mapped to most significant bits (MSBs) of one or more symbols of a composite constellation and the second set of bits is mapped to least significant bits (LSBs) of the one or more symbols of the composite constellation, and wherein the composite constellation is formed from a plurality of lower order constellations; modulate the first set of bits and the second set of bits to generate a set of modulated symbols; and transmit the set of modulated symbols. Numerous other aspects are provided.
MEMORY WITH MULTI-MODE ECC ENGINE
A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.
JOINT POLAR ENCODING OF MULTIPLE PAYLOADS WITH UNEQUAL ERROR PROTECTION
The aspects described herein may enable an apparatus to jointly encode two or more payloads using a single polar encoder device, while providing unequal error protection for the payloads. The apparatus causes a polar encoder to polar encode a first payload and a second payload to generate a polar encoded codeword. The polar encoder is configured to encode one or more bits of the first payload at a first reliability level and encode one or more bits of the second payload at a second reliability level, where the one or more bits of the first payload are associated with a first priority level and the one or more bits of the second payload are associated with a second priority level. The apparatus transmits the polar encoded codeword.