H03M13/356

POLAR CODES AND MODULATION MAPPINGS

Methods, systems, and devices for wireless communication are described. A transmitter, such as a user equipment and/or a base station, may perform polar coding to encode bits. The polar coding may be associated with a plurality of component channels associated with a polar code length. The transmitter may interleave the encoded bits. The transmitter may map the interleaved encoded bits to a modulation symbol. The interleaving and mapping of each encoded bit may be based on an asymmetry of a polar code construction. The transmitter may transmit the interleaved encoded bits based on the mapping.

Parallel bit interleaver
11671118 · 2023-06-06 · ·

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Data processing device and data processing method

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

Method and apparatus for improving reliability of digital communications
11669378 · 2023-06-06 ·

A method and apparatus for improving the reliability of a digital communications system is provided. In accordance with at least one embodiment, power of a transmitted signal is controlled to improve reliability. In accordance with at least one embodiment, timing of a transmitted signal is controlled to improve reliability. In accordance with at least one embodiment, interference is detected. In accordance with at least one embodiment, interference is localized. In accordance with at least one embodiment, combinatorial processing is used to increase reliability. In accordance with at least one embodiment, gradual rekeying is performed. In accordance with at least one embodiment, confirmed stepwise progression rekeying is performed. In accordance with at least one embodiment, transmission detection is provided. In accordance with at least one embodiment, reporting of cryptographic mode utilization is provided.

Signal processing apparatus and signal processing method

A signal processing device includes a distributing unit and a plurality of correcting units with different processing performance, the distributing unit distributes a bit sequence having a first number of bits to the first correcting unit, and a bit sequence having a second number of bits less than the first number of bits to the second correcting unit having lower processing performance than the first correcting unit, the first correcting unit applies error correction processing to the bit sequence having the first number of bits distributed to the first correcting unit, and the second correcting unit applies error correction processing to the bit sequence having the second number of bits distributed to the second correcting unit.

ERROR COALESCING
20220050749 · 2022-02-17 ·

A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

ERROR RATE REDUCTION
20170242747 · 2017-08-24 ·

The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (ERR) data to an amount of received user data, and writing the amount of user data along with the amount of ERR data to a memory.

Coding and modulation apparatus using non-uniform constellation

A coding and modulation apparatus and method are presented. The apparatus (10) comprises an encoder (11) that encodes input data into cell words, and a modulator (12) that modulates said cell words into constellation values of a non-uniform constellation. The modulator (12) is configured to use, based on the total number M of constellation points of the constellation and the signal-to-noise ratio SNR in dB, a non-uniform constellation from a group of constellations comprising one or more of predetermined constellations defined by the constellation position vector w.sub.0 . . . b−1, wherein b=M/4.

Systems and Methods for Allocating Blocks of Memory to Multiple Zones Associated with Corresponding Error Correction Mechanisms
20220035699 · 2022-02-03 ·

Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.

Priority-based channel coding for control information

Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit/receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and/or the second bit level control information group.