H03M13/356

Method of shifting redundancy version for the transmission of a transport block over multiple slots

Where large transport blocks are rate-matched and transmitted on each PUSCH segment using different redundancy versions (RVs), RV cycling with a small number of PUSCH segments might not cover the whole codeword, and/or rate-matching a large TBS across many PUSCH segments into the resource of a single PUSCH segment may lead to an effective coding rate of the self-decodable redundancy versions that is too high. To avoid these issues, the starting position of one or more RVs may be shifted by setting the starting position of a current RV to be the same as an ending position of a previous position, or by scaling the starting position by a value. Alternatively, these issues may be avoided by setting a new starting position for an RV based on the gap from the end of a previous RV to the start of a current RV.

Coding technique for multi-stage control information

Systems and methods for multi-stage downlink control information transmission in a manner that supports existing polar codes are provided. In some embodiments, a method of operation of a radio access node in a cellular communications network to transmit multi-stage downlink control information comprises transmitting a first part of a multi-stage downlink control information in a first Orthogonal Frequency Division Multiplexing (OFDM) symbol and transmitting a second part of the multi-stage downlink control information in a second OFDM symbol that is subsequent to the first OFDM symbol. Cyclic Redundancy Check (CRC) bits are attached to the first part of the multi-stage downlink control information and/or CRC bits are attached to the second part of the multi-stage downlink control information. In some embodiments, the first part and/or the second part of the multi-stage downlink control information is encoded using a polar encoder.

Data Reliability for Extreme Temperature Usage Conditions in DATA Storage
20220029641 · 2022-01-27 ·

Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

PARALLEL BIT INTERLEAVER
20210367618 · 2021-11-25 ·

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Data processing apparatus and data processing method
11177832 · 2021-11-16 · ·

The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

Receiving system and method for processing digital broadcast signal in the receiving system

A transmitting system, receiving system, and a method of processing broadcast signals are disclosed. The method for processing a broadcast signal in a broadcast receiver comprises receiving a DTV signal including a data group, the data group including mobile service data, segmented known data sequences, long known data sequences and transmission parameter data, compensating carrier frequency offset of the DTV signal and channel-equalizing the carrier frequency offset compensated DTV signal using at least one of the long known data sequences and segmented known data sequences in the data group of the DTV signal, wherein the channel-equalizing includes performing a Error Correction (FEC) decoding on data located between the segmented known data sequences, and estimating Channel Impulse Response (CIR) using the FEC decoded data as known data.

MEMORY DEVICE EQUIPPED WITH DATA PROTECTION SCHEME
20220004325 · 2022-01-06 ·

The present disclosure relates to a memory device comprising a hybrid memory portion in turn comprising a main nonvolatile memory and an auxiliary nonvolatile memory, and a controller configured to store data information in the main nonvolatile memory. The controller of the present disclosure comprises a parity engine configured to accumulate temporary parity information in the auxiliary nonvolatile memory, the parity information being associated with the data information stored in the main nonvolatile memory; when the parity information accumulated in the auxiliary nonvolatile memory is complete, the parity engine is further configured to transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory. A related apparatus and a related method are also disclosed.

Data processing apparatus and data processing method
11218170 · 2022-01-04 · ·

The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

Transmission method and reception device
11218169 · 2022-01-04 · ·

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

Error correction system
11791009 · 2023-10-17 · ·

An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.