Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

The present application provides a data processing method, a data processing device, a decoder, a network device and a computer-readable storage medium. The data processing method includes: classifying log likelihood ratio (LLR) elements according to a modulation mode, a preset decoder quantization threshold and a signal-to-noise ratio, to obtain a classification result; extracting feature information of each category in the classification result; calculating to obtain a scale factor according to the feature information of each category; and scaling the LLR elements according to the scale factor.

An LDPC decoding method of a received signal including a plurality of received symbols is provided. A decoding apparatus selects a perturbation space in which perturbation is to be performed based on a code length of the received signal and a maximum number of perturbation rounds indicating a number of perturbation rounds that can be performed, and performs a perturbation round. The decoding apparatus performs perturbation on a corresponding received symbol among the plurality of received symbols in each perturbation round, and decodes the received signal on which the perturbation has been performed. The decoding apparatus determines that decoding is successful when there is a perturbation round in which a decoding result of the received signal satisfies a predetermined condition.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

A method of soft decoding received signals. The method comprising defining quantisation intervals for a signal value range, determining a number of bits in each quantisation interval that are connected to unsatisfied constraints, providing, the number of bits in each quantisation interval that are connected to unsatisfied constraints, as an input to a trained model, wherein the trained model has been trained to cover an operational range of a device for soft decoding of signals, determining, using the trained model, a log likelihood ratio for each quantisation interval, and performing soft decoding using the log likelihood ratios.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.

A decoder that is a decoding apparatus includes an error-correction decoder that executes error correction decoding processing of iteratively performing decoding processing with a window size and the number of decoding iterations indicated by decoding parameters, on received data converted into a spatially coupled low-density parity-check code, and a decoding parameter control unit that updates the decoding parameters on the basis of a decoding result obtained by the iteratively executed decoding processing.

Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.