Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

An embodiment method includes receiving, by a first user equipment (UE), a message, for a second UE, transmitted over a plurality of resource blocks (RBs) on behalf of a communications controller and determining a plurality of log-likelihood ratios (LLRs) in accordance with the received plurality of RBs. The method also includes transmitting, a subset of the determined LLRs to the second UE.

Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.

Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

Disclosed are methods, systems and devices for decoding data read from a memory device, including receiving noisy data from a first memory location included in a word line zone of the memory device, identifying the word line zone and a prior successful decoder parameter associated with the word line zone, decoding the noisy data using the prior successful decoder parameter used in a prior successful decoding with respect to a second memory location included in the same word line zone, determining whether the decoding based on the prior successful decoder parameter has succeeded, maintaining, upon a determination that the decoding has succeeded, the prior successful decoder parameter as a decoder parameter for the first memory location, and decoding, upon a determination that the decoding operation has failed, the noisy data read from the first memory location by using another decoder parameter selected from a set of predefined decoder parameters.

Disclosed are devices, systems and methods for improving a quality of service of an adaptive soft decoder in a non-volatile memory device. An example method includes selecting, based on current operating conditions of the non-volatile memory device, a first decoder parameter set from an ordered plurality of decoder parameter sets, each decoder parameter set corresponding to a distinct operating condition of the non-volatile memory device and comprising parameters related to a soft decoding operation; performing, based on the first decoder parameter set, the soft decoding operation; upon a determination that the soft decoding operation has succeeded, reordering the ordered plurality of decoder parameter sets to place the first decoder parameter set at a start of the ordered plurality of decoder parameter sets, and otherwise, performing the soft decoding operation based on a second decoder parameter set selected from the ordered plurality of decoder parameter sets.

There are provided an error correction circuit and a method of operating the same. The circuit may performs error correction decoding within a maximum global iteration number G, and may include a mapper configured to generate read values quantized into g+1 levels to be used in a g-th global iteration by using read values corresponding to g number of read voltages, a node processing component configured to perform error correction decoding, during the g-th global iteration, by using the read values quantized into g+1 levels, a syndrome information management component configured to manage syndrome information corresponding to the g-th global iteration, and a global iteration control component configured to, when error correction decoding fails in the g-th global iteration, determine whether the syndrome information corresponding to the g-th global iteration satisfies a condition defined in a global iteration skip policy, and decide whether to skip (g+1)th to (G1)th global iterations.

Disclosed herein are memory devices, systems, and methods of content-aware decoding of encoded data. In one aspect, an encoded data chunk is received and one or more characteristics, such as source statistics, are determined. A similar data chunk (that may, e.g., contain data of a similar type) with comparable statistics may be sought. The similar data chunk may, for example, have source statistics that are positively correlated to the source statistics of the encoded data chunk to be decoded. Decoder parameters for the encoded data may be set to correspond with decoder parameters suited to the similar data chunk. The encoded data chunk is decoded using the new decoder parameters. Decoding encoded data based on content can enhance performance, reducing decoding latency and/or power consumption.