Devices, systems, and methods that reduce the latency of detecting that a codeword is uncorrectable are disclosed and described. Such devices, systems, and methods allow the determination that a codeword is uncorrectable prior to determining error locations in the codeword, thus eliminating the need for such an error location search.

An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.

A method for checking a signal transmission of a specified message with a number of d bits from a sender to a receiver by a control unit using a linear block code generated via a coding tool, a channel model, and a specified linear feedback shift register, which is parameterized via a generator polynomial, wherein the residual error probability of different Markov-modulated Bernoulli processes is calculated, where boundary conditions for signal transmission can be specified by using a characterizing Markov-modulated Bernoulli process and also a linear feedback shift register, where integration of the calculation of the residual error probability is performed in a dynamic, intelligent control circuit such that the respective residual error probabilities can be determined for different generator polynomials.

A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Methods, systems, and devices for wireless communication are described. The examples described herein may enable a decoder to determine path metrics for various decoding paths based on identified frozen bit locations of a polar code. The path metric for a decoding path may be based on bit metrics determined for the identified frozen bit locations along the decoding path. Once the path metrics and bit metrics are determined, the decoder may compare these metrics to threshold criteria and determine whether to discard decoding paths based on the comparison. The techniques described herein for discarding decoding paths may allow the decoder to discard, prune, or disqualify certain decoding paths that are unlikely to provide an accurate representation of bits received from another device. Consequently, the decoder may be able to save power by terminating a decoding process early (i.e., early termination) if all paths are discarded, pruned, or disqualified.

A decoder can receive an indication that a portion of a codeword has been decoded during a decoding operation. The decoder can determine a group of candidate output values of the decoding operation for the portion of the codeword, and eliminate one or more candidate output values from the group of candidate output values based on a decoded check code for each of the group of candidate output values. In response to determining that all of the candidate output values have been eliminated from the group of candidate output values, the decoder can terminate the decoding operation.

The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.

A memory system and a method for operating the memory system, in which the memory system includes a semiconductor memory device for storing data, and for reading and outputting the stored data in a read operation, and a controller controlling the semiconductor memory device in the read operation, and sequentially performing first and second decoding operations on the data output from the semiconductor memory device, wherein the controller updates and stores a bin label codeword in the second decoding operation, and backs up and stores a start bin label codeword in the bin label codeword.

The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.