An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.

A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises providing an indication of reliability of the read bits, and, based on said indication of reliability, iteratively soft decoding the read bits in order to obtain said information bits. Said soft decoding comprises, at each iteration of the soft decoding, if the current number of iterations has reached a predetermined number of iterations indicative of an admitted latency of the solid state drive, and if no information bits having an error rate below a predetermined error rate have been obtained, providing a further indication of reliability of the read bits, and iteratively soft decoding the read bits based on said further indication of reliability.

A corresponding solid state drive is also proposed.

A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.

The present disclosure relates to a 5G or pre-5G communication system to be provided to support a data transmission rate higher than that of a 4-G communication system, such as LTE, and subsequent communication systems. An apparatus according to one embodiment of the present invention can comprise: a first grouping unit for performing repeated decoding by using an outer decoder and an inner decoder, and grouping, in correspondence to a decoding order, a bit stream, which is received from the outer decoder, from a receiver of a system using binary irregular repeat partial accumulate codes to the inner decoder device; an LLR symbol selection unit for calculating indices of grouped bits having the maximum probability value among the grouped bits, and selecting and outputting a predetermined number of grouped bit LLR values by using the indices of the grouped bits having the maximum probability value; an LLR symbol conversion unit for converting the grouped bit LLR values outputted from the LLR symbol selection unit into symbol LLR values, and outputting the same; a Bahl-Cocke-Jelinek-Raviv (BCJR) processing unit for performing a BCJR algorithm operation on the symbol LLR values; a bit LLR calculation unit for converting an output of the BCJR processing unit into bit LLR values; and a second bit grouping unit for grouping the bit LLR values by predetermined bit units.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.