Patent classifications
H03M13/3761
Dynamic mapping of logical to physical memory for increased performance
Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.
Method and system for facilitating a storage server with hybrid memory for journaling and data storage
One embodiment provides a system which facilitates data management. During operation, the system receives, by a first memory device, data to be written to a first non-volatile memory of the first memory device and to a second non-volatile memory of a storage drive distinct from the first memory device. The system performs, by the first memory device on the received data, a compression operation and erasure code (EC)-encoding to obtain a compressed EC codeword. The system initiates a first write operation and a second write operation in parallel, wherein the first write operation comprises writing a first part of the compressed EC codeword to the first non-volatile memory, and wherein the second write operation comprises writing the first part of the compressed EC codeword to the second non-volatile memory.
Reliability coding with reduced network traffic
This disclosure describes techniques that include implementing network-efficient data durability or data reliability coding on a network. In one example, this disclosure describes a method that includes generating a plurality of data fragments from a set of data to enable reconstruction of the set of data from a subset of the plurality of data fragments; storing, across a plurality of nodes in a network, the plurality of data fragments, wherein storing the plurality of data fragments includes storing the first fragment at a first node and the second fragment at a second node; and generating, by the first node, a plurality of secondary fragments derived from the first fragment to enable reconstruction of the first fragment from a subset of the plurality of secondary fragments; and storing the plurality of secondary fragments from the first fragment across a plurality of storage devices included within the first node.
Datacenter relocation utilizing storage carriers and erasure coding
Computer implemented systems and methods for migrating datacenter data include providing a quantity of carriers having a data storage capacity, receiving, by the quantity of carriers, a quantity of data stored in a first data storage system having a first location and including erasure coded data blocks. The quantity of carriers migrates to a second data storage system having a second location; and transmits the quantity of data to the second data storage system.
Transmitter and method for generating additional parity thereof
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.
Dynamically variable error correcting code (ECC) system with hybrid rateless reed-solomon ECCs
Example apparatus and methods control whether and when hybrid rateless Reed Solomon (RS) error correcting codes (ECC) for a message are produced, stored, and distributed. The control may be based on a property (e.g., reliability, error state, speed) of a message recipient. Example apparatus and methods may also control whether and when fountain codes for the message are produced, stored, and distributed. Once again, the control may be based on a property of a message or ECC recipient. Both the hybrid rateless RS ECC and the fountain codes may be produced from data stored in a modified RS matrix. The modified RS matrix may store row-centric error detection codes (EDC) instead of conventional cyclic redundancy check (CRC) characters. The modified RS matrix may store column-centric ECC that may be produced serially. Different types or numbers of ECC may be produced, stored, and provided for different messages stored at different recipients.
NETWORK CODING DESIGN
An apparatus, such as a base station, may determine channel conditions associated with at least two carriers on which communication with another apparatus is configured. The apparatus may encode a dataset into a set of protocol data units (PDUs) using fountain coding based on the channel conditions. The apparatus may send a first subset of the set of PDUs to the other apparatus on a first carrier of the at least two carriers. The apparatus may send a second subset of the set of PDUs to the other apparatus on a second carrier of the at least two carriers. Another apparatus, such as a user equipment (UE), may receive the set of PDUs from the apparatus over the at least two carriers, and may decode the set of PDUs to obtain a dataset using fountain coding.
Maintaining failure independence for storage of a set of encoded data slices
A method includes detecting a storage error associated with a first memory device of a storage unit of a set of storage units, where data is error encoded into a set of encoded data slices and stored in a plurality of memory devices of the set of storage units, and where the plurality of memory devices includes the first memory device. The method further includes determining attributes associated with the first memory device and determining attributes of other memory devices of the plurality of memory devices. The method further includes selecting a memory device from the other memory devices based on the attributes of the memory device comparing favorably to the attributes associated with the first memory device. The method further includes rebuilding an encoded data slice associated with the storage error and storing the rebuilt encoded data slice in the selected memory device.
Stripe merging method and system based on erasure codes
A stripe merging method and system based on erasure codes are provided. A StripeMerge-P algorithm is used first to determine alignment information of parity chunks of erasure code stripes based on a preprocessed hash table. Through a greedy strategy, erasure code stripe pairs to be merged are selected for merging. Through the hash table, location information of the parity chunks is directly looked up, so that no additional computing overhead is required, and the overhead of selecting and merging the erasure code stripe pairs is further reduced through the combination with the greedy strategy.
Selective erasure decoding for memory devices
Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.