H03M13/3776

PREDICTIVE CONTEXT-BASED DECODER CORRECTION
20240420702 · 2024-12-19 ·

Disclosed in some examples are methods, systems, and machine-readable mediums for utilizing context information to create decoding feedback information to improve decoder accuracy and/or performance. In some examples, the context information is from layers of a network stack above the layers in which the decoders are present. The context information may be or be based upon information about previously received and decoded data and/or information about the sender to provide decoding feedback information to the decoder that is used either to correct a previous decoding error or to inform the decoder on which of a plurality of decoding choices is more likely to be correct. This may increase decoding performance by decreasing errors and in some examples, reducing the complexity of choices by eliminating certain decoding possibilities and thus increasing decoder efficiency.

Accelerated erasure coding system and method
12199637 · 2025-01-14 · ·

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Using parity data for concurrent data authentication, correction, compression, and encryption
09760439 · 2017-09-12 · ·

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Generic encoder for low-density parity-check (LDPC) codes

Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.

DECODING ALGORITHM WITH ENHANCED PARITY CHECK MATRIX AND RE-ENCODING SCHEME FOR LDPC CODE
20170070239 · 2017-03-09 · ·

A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

EARLY TERMINATION METHOD WITH RE-ENCODING SCHEME FOR DECODING OF ERROR CORRECTION CODE
20170070243 · 2017-03-09 · ·

An early termination method with a re-encoding scheme for decoding of error correction codes is disclosed. The method includes the steps of: A. receiving soft values; B. processing hard decision on the soft value to determine a codeword; C. separating the codeword into a data part and a first parity part; D. re-encoding the data part to get a second parity part; E. checking if the first parity part and the second parity part are equivalent; and F. if a result of step E is yes, stopping decoding the codeword; if the result of step E is no, processing a decoding algorithm on the codeword. By this method, the received codeword still can be correctly decoded if there are many errors in the parity region and its decoding performance can be improved.

ACCELERATED ERASURE CODING SYSTEM AND METHOD
20250096818 · 2025-03-20 ·

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION
20170024280 · 2017-01-26 · ·

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

SIGNAL MULTIPLEXING DEVICE AND SIGNAL MULTIPLEXING METHOD USING LAYERED DIVISION MULTIPLEXING

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

ACCELERATED ERASURE CODING SYSTEM AND METHOD
20170005671 · 2017-01-05 · ·

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.