A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.

A receiver for receiving data in a broadcast system includes a broadcast receiver that receives, via the broadcast system, a receiver input data stream including plural channel symbols represented by constellation points in a constellation diagram. A demodulator demodulates the channel symbols into codewords and a decoder decodes the codewords into output data words. A broadband receiver obtains redundancy data via a broadband system, the redundancy data for a channel symbol including one or more least robust bits of the channel symbol or a constellation subset identifier indicating a subset of constellation points including the constellation point representing the channel symbol. The demodulator and/or the decoder is configured to use the redundancy data to demodulate the respective channel symbol and to decode the respective codeword, respectively.

There is provided a method of recursive sequential list decoding of a codeword of a polar code comprising: obtaining an ordered sequence of constituent codes usable for the sequential decoding of the polar code, representable by a layered graph; generating a first candidate codeword (CCW) of a first constituent code, the first CCW being computed from an input model informative of a CCW of a second constituent code, the first constituent code and second constituent code being children of a third constituent code; using the first CCW and the second CCW to compute, by the decoder, a CCW of the third constituent code; using the CCW of the third constituent code to compute a group of symbol likelihoods indicating probabilities of symbols of a fourth (higher-layer) constituent code having been transmitted with a particular symbol value, and using the group of symbol likelihoods to decode the fourth constituent code.

There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.

There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.

A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.

Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Techniques for achieving reductions in cost of encoding and decoding operations used in DNA data storage systems to facilitate reducing errors in those encoding and decoding operations while accounting for a code structure used during the encoding and decoding by constructing and using insertion-deletion-substitution (IDS) trellises for multiple traces are disclosed. A DNA sequencing channel is used to randomly sample and sequence DNA strands to generate noisy traces. Multiple trellises are independently constructed for each respective noisy trace. A forward-backward algorithm is run on each trellis to compute posterior marginal probabilities for vertices included in each trellises. An estimate of the data message sequence is then computed.