Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Digital data archival methods and systems are described, providing controlled and verifiable information destruction. In one embodiment, the method comprises storing digitally encoded information, wherein the information is encoded as a sequence of numbers or symbols using parameters defining an associated error correction ability of an error correcting algorithm based on a lifetime of the digitally encoded information. Errors are periodically added to the sequence of numbers or symbols, such that the digitally encoded information is recoverable from the sequence of numbers or symbols during the defined lifetime, and after a total of number of added errors exceeds the associated error correction ability, the digitally encoded information cannot be retrieved.

Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.

A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.

A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.