A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

The system and method described provide correction of modulation symbol errors which may occur during audio pairing of computing devices. The transmission between the computing devices comprises a six modulation symbol (24 bit) token containing transaction information and a two check symbol (8 bit) cyclic redundancy check (“CRC”). Error probabilities of symbols are be used to identify probable symbol error locations and the number of errors contained in the received transmission during the symbol decoding process. If there is a single modulation symbol error, the 16 possible combinations of bit values are cycled through until one combination passes the CRC check. If there are two modulation symbol errors, the 256 possible combinations of bit values are cycled through until two combinations pass the CRC check.

The system and method described provide correction of modulation symbol errors which may occur during audio pairing of computing devices. The transmission between the computing devices comprises a six modulation symbol (24 bit) token containing transaction information and a two check symbol (8 bit) cyclic redundancy check (“CRC”). Error probabilities of symbols are be used to identify probable symbol error locations and the number of errors contained in the received transmission during the symbol decoding process. If there is a single modulation symbol error, the 16 possible combinations of bit values are cycled through until one combination passes the CRC check. If there are two modulation symbol errors, the 256 possible combinations of bit values are cycled through until two combinations pass the CRC check.

Provided is an error correction decoding device including an inner code iterative decoding circuit, a parameter generation circuit, and a first control circuit. The first control circuit is configured to: receive, as parameters, a threshold and a maximum iteration count which are generated by the parameter generation circuit; and compare, when an iteration count does not reach the maximum iteration count, a non-zero-value count sequentially output from the inner code iterative decoding circuit and the threshold set for each iteration count, and stop an iterative operation by the inner code iterative decoding circuit when a result of the comparison satisfies a stopping condition set in advance.

Provided is an error correction decoding device including an inner code iterative decoding circuit, a parameter generation circuit, and a first control circuit. The first control circuit is configured to: receive, as parameters, a threshold and a maximum iteration count which are generated by the parameter generation circuit; and compare, when an iteration count does not reach the maximum iteration count, a non-zero-value count sequentially output from the inner code iterative decoding circuit and the threshold set for each iteration count, and stop an iterative operation by the inner code iterative decoding circuit when a result of the comparison satisfies a stopping condition set in advance.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an encoding device may determine a least reliable subset of information bits included in a set of information bits that includes a predefined active set of information bits to be encoded; may determine a codeword bit to be added to a codeword based at least in part on the least reliable subset of information bits, wherein adding the codeword bit to the codeword improves reliability of the least reliable subset of information bits; may add the codeword bit to the codeword; and may transmit the codeword. Numerous other aspects are provided.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an encoding device may determine a least reliable subset of information bits included in a set of information bits that includes a predefined active set of information bits to be encoded; may determine a codeword bit to be added to a codeword based at least in part on the least reliable subset of information bits, wherein adding the codeword bit to the codeword improves reliability of the least reliable subset of information bits; may add the codeword bit to the codeword; and may transmit the codeword. Numerous other aspects are provided.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.