The present disclosure relates to a decoding method. The decoding method includes a sequentially determining series of source bits from a codeword by performing a first decoding operation and a second decoding operation. For instance, a series of N source bits may be divided into a first bit group of X source bits and a second bit group of Y source bits. The initial X source bits are sequentially determined in the first decoding operation and the remaining Y source bits are sequentially determined in the second decoding operation. The first decoding operation includes sorting at least 2L reliability values, which are calculated from L bit sequences, where L is an integer greater than 0. The second decoding operation includes determining a source bit in each of the L bit sequences, based on the at least 2L reliability values.

The present disclosure relates to a decoding method. The decoding method includes a sequentially determining series of source bits from a codeword by performing a first decoding operation and a second decoding operation. For instance, a series of N source bits may be divided into a first bit group of X source bits and a second bit group of Y source bits. The initial X source bits are sequentially determined in the first decoding operation and the remaining Y source bits are sequentially determined in the second decoding operation. The first decoding operation includes sorting at least 2L reliability values, which are calculated from L bit sequences, where L is an integer greater than 0. The second decoding operation includes determining a source bit in each of the L bit sequences, based on the at least 2L reliability values.

Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.

The present disclosure provides a decoding system and method. The decoding system comprises a first decoder and a second decoder. The first decoder is configured to generate an intermediate decoding data by decoding a code data. The second decoder, coupled to the first decoder, wherein the second decoder is configured to generate a plain data by decoding the intermediate decoding data.