A controller of a memory system performs a soft decoding without additional reads. The controller applies each of read voltages to cells to obtain a corresponding cell count and corresponding data, stores the obtained data, and processes the stored data. The controller determines a set of parameters, based on (i) the read voltages, (ii) cell counts corresponding to the read voltages and (iii) a non-negative regularization parameter. The controller estimates an optimal read voltage based on the set of parameters, generates log-likelihood ratio (LLR) values using the processed data and the optimal read voltage and performs soft decoding using the LLR values.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Embodiments of the application provides a method for encoding. The method includes: receiving a to-be-encoded data block; encoding the data block at an aggregation level of 2L, where a formula used during the encoding is as follows: $\begin{array}{c}\left[\begin{array}{cc}{\stackrel{.}{u}}_{2L}& {\stackrel{.}{u}}_L\end{array}\right]\left[\begin{array}{cc}{G}_{\mathrm{LN}}& 0\\ G_{\mathrm{LN}}& G_{\mathrm{LN}}\end{array}\right]=.Math.\begin{array}{cc}{\stackrel{.}{C}}_{2L}& {\stackrel{}{C}}_{}\end{array}\end{array}$

Embodiments of the application provides a method for encoding. The method includes: receiving a to-be-encoded data block; encoding the data block at an aggregation level of 2L, where a formula used during the encoding is as follows: $\begin{array}{c}\left[\begin{array}{cc}{\stackrel{.}{u}}_{2L}& {\stackrel{.}{u}}_L\end{array}\right]\left[\begin{array}{cc}{G}_{\mathrm{LN}}& 0\\ G_{\mathrm{LN}}& G_{\mathrm{LN}}\end{array}\right]=.Math.\begin{array}{cc}{\stackrel{.}{C}}_{2L}& {\stackrel{}{C}}_{}\end{array}\end{array}$

In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.

In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.

A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

A transmitter (200) generates (602) an encoded vector (404) by encoding (406) a data vector (402), the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits (604) a signal representing the encoded vector over a communication channel. A receiver (300) determines (702) a vector estimate (502) from the signal and recovers (716) the data vector from the vector estimate by sequentially decoding (706, 710, 714) the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.