A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.

Communication systems are described that use unequally spaced constellations that have increased capacity compared to conventional constellations operating within a similar SNR band. One embodiment is a digital communications system including a transmitter transmitting signals via a communication channel, the transmitter including a coder capable of receiving user bits and outputting encoded bits at a rate, a mapper capable of mapping encoded bits to symbols in a constellation, and a modulator capable of generating a modulated signal for transmission via the communication channel using symbols generated by the mapper, wherein the constellation is unequally spaced and characterizable by assignment of locations and labels of constellation points to maximize parallel decode capacity of the constellation at a given signal-to-noise ratio so that the constellation provides a given capacity at a reduced signal-to-noise ratio compared to a uniform constellation that maximizes the minimum distance between constellation points of the uniform constellation.

The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

Example systems, read channels, and methods provide bit value detection from an encoded data signal using a neural network soft information detector. The neural network detector determines a set of probabilities for possible states of a data symbol from the encoded data signal. A soft output detector uses the set of probabilities for possible states of the data symbol to determine a set of bit probabilities that are iteratively exchanged as extrinsic information with an iterative decoder for making decoding decisions. The iterative decoder outputs decoded bit values for a data unit that includes the data symbol.

A communication unit for performing soft-decision demodulation comprises a receiver that receives a transmitted signal having a first set of bits comprising k bits, selected from a set of 2.sup.k possible signals according to values of the k bits, and a second set of bits comprising Q.sub.m bits based on a phase rotation of the transmitted signal selected from a set of 2.sup.Qm possible rotations. The receiver comprises: a demodulator comprising a bank of 2.sup.k correlators and is configured to: detect a transmission of each possible transmitted signal, and output 2.sup.k phases of the correlator outputs as a third set of inputs. A de-mapper circuit receives the third set of inputs: determines statistics derived from a number of aggregated correlator output phase distributions of the third set of inputs; and calculates and outputs a second set of aposteriori soft bits comprising Q.sub.m soft bits.

A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.

A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.