H03M13/6331

MESSAGE PASSING ALGORITHM DECODER AND METHODS
20170265213 · 2017-09-14 ·

Methods and devices are disclosed for receiving and detecting sparse data sequences using a message passing algorithm (MPA) with early propagation of belief messages. Such data sequences may be used in wireless communications systems supporting multiple access, such as sparse code multiple access (SCMA) systems. The determination and passing of one or more messages for an edge between a function node and a variable node in a factor graph representation of the system may be performed in serial with determined values available early for subsequent computations. The serial computations may be scheduled based on various factors.

Systems and methods for Nyquist error correction
11368170 · 2022-06-21 · ·

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Decoding apparatus, decoding method, and non-transitory computer readable medium
11336306 · 2022-05-17 · ·

A decoding apparatus includes a multi-input branch metric calculation unit configured to calculate, by using a branch label corresponding to a path extending toward a state S at a time point N in a trellis diagram and a plurality of reception signal sequences, a branch metric in the state S, a path metric calculation unit configured to calculate a path metric in the state S at the time point N, and a surviving path list memory configured to store path labels corresponding to L path metrics among a plurality of calculated path metrics. The path metric calculation unit generates a path label in the state S at the time point N by combining the branch label with a path label in each of the states at the time point N−1 and the surviving path list memory outputs path labels corresponding to L path metrics.

BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH FREQUENCY DOMAIN INFORMATION PROCESSING

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block that processes the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

PHYSICAL LAYER LOW-LATENCY FORWARD ERROR CORRECTION

Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques minimize latency in the PHY, being optimal for Gen-Z systems. The FEC techniques can provide improvements over existing FEC schemes that employ large code word sizes and experience high latency.

Multiple detector data channel and data detection utilizing different cost functions

Systems and methods are disclosed for a multiple detector data channel and data detection utilizing different cost functions. For example, a digital data channel system can have multiple data detectors where each data detector implements a distinct cost function for detecting data. A cost function analyzer can then selectively choose decisions from the multiple data detectors to generate a data sequence. In some examples, a dual detector system may have one detector implement a Soft-Output Viterbi Algorithm (SOVA) cost function and another detector implement a peak detection algorithm. Further, in some embodiments, the cost function analyzer can implement multiple selection criteria to determine which decisions to include in a data sequence from the multiple data detectors.

RECEIVER AND RECEIVE METHOD FOR A PASSIVE OPTICAL NETWORK
20220286332 · 2022-09-08 ·

A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.

Deep neural network a posteriori probability detectors and media noise predictors for one- and two-dimensional magnetic recording

A deep neural network (DNN) media noise predictor configured for one-dimensional-magnetic (1DMR) recording or two-dimensional-magnetic (TDMR) is introduced. Such architectures are often combined with a trellis-based intersymbol interference (ISI) detection component in a turbo architecture to avoid the state explosion problem by separating the inter-symbol interference (ISI) detection and media noise estimation into two separate detectors and uses the turbo-principle to exchange information between them so as to address the modeling problem by way of training a DNN-based media noise estimators. Thus, beneficial aspects include a reduced bit-error rate (BER), an increased areal density, and a reduction in computational complexity and computational time.

BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH NEURAL NETWORK BASED DETECTION
20220224361 · 2022-07-14 · ·

The technology relates to bandwidth constrained communication systems with neural network based detection. In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises: a transmitter comprising an error control code encoder, a pulse-shaping filter, and a first interleaver; a communication channel; and a receiver comprising a neural network processing block that processes a received signal. The error control code encoder can append redundant information onto the signal. The pulse-shaping filter can intentionally introduce memory into the signal in the form of inter-symbol interference. The first interleaver can change a temporal order of the symbols in the signal. The error control code encoder can be a low-density parity-check (LDPC) error control code encoder. The neural network can be trained with positive mappings between transmitted and decoded training signals, or negative mappings between training signals and a null space of an LDPC generation matrix.

Viterbi equalizer with soft decisions

A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.