H03M13/6337

Wireless receiver
10193659 · 2019-01-29 · ·

The present invention relates to a method and apparatus for channel estimation between a transmitter and a receiver in a wireless communications system. In one arrangement, the method comprises: receiving at the receiver a first sequence of bits representing a first sequence of coded symbols transmitted over the communications channel; decoding the first sequence of coded symbols using maximum-likelihood based decoding including: generating traceback outcomes by tracing backwards the first sequence of bits through a maximum-likelihood based traceback path, the traceback outcomes including a first portion associated with a first traceback depth and a second portion associated with a second traceback depth that is deeper than the first traceback depth; generating a channel estimate of the communications channel based on the first portion of the traceback outcomes; and generating an estimate of at least some information bits coded in the first sequence of coded symbols based on the second portion of the traceback outcomes.

INDICATING A NUMBER OF COPIED INFORMATION BITS IN A RETRANSMISSION
20190028119 · 2019-01-24 ·

Methods, systems, and devices are described for wireless communications. A transmitting device may generate first encoded bits by encoding first information bits using a polar code of a first size, N, and transmit the first encoded bits to a receiving device. After determining the receiving device failed to decode the encoded bits, the transmitting device may generate second encoded bits by encoding the first information bits using a polar code of a second size, 2N. In some cases, the transmitting device may use the first encoded bits and one or more copied information bits to generate the second encoded bits. The transmitting device may transmit the second encoded bits to the receiving device, along with an indication of the number of copied information bits used to generate the second encoded bits. The number of copied information bits may be based on changing channel conditions or transmission parameters.

Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

MULTI-CHANNEL MEMORY OPERATIONS BASED ON BIT ERROR RATES

In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

Multi-channel memory operations based on bit error rates

In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

Systems and methods for enhanced data recovery in a solid state memory system
09996416 · 2018-06-12 · ·

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

WIRELESS TRANSMISSION METHOD FOR SIMPLE RECEIVERS
20180152264 · 2018-05-31 ·

Embodiments provide a method for transmitting, according to which the payload data included in the data packet is provided with at least one indicator, such that a degree of interference of the received data (e.g. already decided bits) provided by the receiver for receiving data packets (e.g. a simple cost-effective radio chip) can be determined based on the at least one indicator, such that the determined degree of interference can be considered during channel decoding of the channel-coded payload data for increasing efficiency of channel decoding.

PROGRESSIVE POLAR CHANNEL CODING IN FLASH MEMORY AND COMMUNICATIONS
20180091174 · 2018-03-29 ·

A method for storing data in a solid state device includes applying polar coding to generate channels including perfect channels, useless channels, and channels that are neither perfect nor useless. Some data is encoded using the perfect channels. A predetermined value is encoded using the useless channels. The other channels are divided into groups, depending upon a quality of each channel. Other data is encoded using the channels that are neither perfect nor useless using a different coding technique. This coding technique is applied to the same quality channels using several polar codewords, in parallel. Decoding is carried in a progressive parallel manner where the other coding technique assists the decoding of some polar codewords based on correct results from other polar codewords that were successfully decoded. The encoded data to be stored is written into the solid state device or transmitted.

Forward error correction with turbo/non-turbo switching

A forward error correction and differentially encoded signal obtained via a communication channel is supplied to a soft-input soft-output (SISO) differential decoder that is bi-directionally coupled to a SISO forward error correction decoder. Over a first portion of a plurality of decoding iterations of the differentially encoded signal, the SISO differential decoder and the SISO forward error correction decoder are operated in a turbo decoding mode in which decoded messages generated by the SISO differential decoder are supplied to the SISO forward error correction decoder and forward error correction messages are supplied to the differential decoder. Over a second portion of the plurality of decoding iterations of the differentially encoded signal, the SISO forward error correction decoder is operated in a non-turbo decoding mode without any messages passing to and from the SISO differential decoder. Decoder output is obtained from the SISO forward error correction decoder.

GENERALIZED SYNDROME WEIGHTS
20180032396 · 2018-02-01 · ·

A device includes a memory device and a controller. The controller is configured to determine, based on data read from the memory device, a first count of bits of the data that are associated with at least a first number of unsatisfied parity checks of the data and a second count of bits of the data that are associated with at least a second number of unsatisfied parity checks of the data. The controller is further configured to perform one or more operations based at least partially on the first count and the second count.