Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

To obtain a signal quality evaluation value capable of having a high correlation to an error rate and high accuracy for a reproduction signal of high density recording. For the object, an estimated value of a path selection error rate is obtained on the basis of a distribution of a path metric difference between a maximum likelihood path at each time, which is a detection path in maximum likelihood decoding in a PRML decoding system and a second path having a second highest likelihood. Further, an average error bit number in erroneous detection is obtained from a bit difference number between the maximum likelihood path and the second path at the time of path selection of each time in the maximum likelihood decoding. In addition, an estimated bit error rate is obtained from results and an evaluation value according to the estimated bit error rate is generated.

An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.

Methods, systems, and devices are described for wireless communications. A transmitting device may generate first encoded bits by encoding first information bits using a polar code of a first size, N, and transmit the first encoded bits to a receiving device. After determining the receiving device failed to decode the encoded bits, the transmitting device may generate second encoded bits by encoding the first information bits using a polar code of a second size, 2N. In some cases, the transmitting device may use the first encoded bits and one or more copied information bits to generate the second encoded bits. The transmitting device may transmit the second encoded bits to the receiving device, along with an indication of the number of copied information bits used to generate the second encoded bits. The number of copied information bits may be based on changing channel conditions or transmission parameters.

Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.

A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple versions.

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

A system includes a first sync mark detector circuit operable to apply a first sync mark detection algorithm to search a received media sector and overhead for a second sync mark after a failure to identify a first sync mark. A second sync mark detector circuit operable to apply a second sync mark detection algorithm to search the received media sector and overhead for the second sync mark. An anchor point identification circuit identifies an anchor point in the received media sector. A retry controller circuit causes a re-read of the received media sector and overhead when the first sync mark detector circuit fails to identify the first sync mark, and aligns the received media sector to yield an aligned media sector. A data processing circuit recovers an original user data set from the aligned media sector.