An apparatus (e.g., receive chain) for wireless communications may perform de-interleaving, de-rate matching, and hybrid automatic repeat request (HARQ) combining in a single step. The apparatus may include a data pool configured to store HARQ log likelihood ratio (LLR) data from previous transmissions. The apparatus may include a HARQ onload controller configured to load HARQ LLR data from the HARQ data pool into a HARQ buffer. The apparatus may include an LLR buffer configured to store received demodulated, interleaved, and rate matched LLR data. The apparatus may include a plurality of processing engines configured to, starting at different locations of the LLR buffer: receive new input data from the LLR buffer; combine the HARQ LLR data from the HARQ buffer with the new input data to generate de-interleaved, de-rate matched, and HARQ combined data; and write the de-interleaved, de-rate matched, and HARQ combined data into the HARQ buffer.

Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.

The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.

A method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. A number N of inner code blocks needed to transmit the transport block is determined. A number M—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. The transport block may then be segmented and encoded according to the calculated encoding parameters.

The present disclosure provides a method and an apparatus for sequence determination, a device and a storage medium. The method for sequence determination includes: mapping a first bit sequence having a length of K bits to a specified position based on M_index to obtain a second bit sequence; applying Polar encoding to the second bit sequence to obtain a Polar encoded bit sequence; and selecting T bits based on the Polar encoded bit sequence as a bit sequence to be transmitted, where K and T are both non-negative integers and K≤T.

A transmitting device is described for a communication system. The transmitting device obtains an information message comprising information bits addressed for a receiving device and encodes the information message to obtain a codeword. The transmitting device rate-matches the codeword to produce a rate-matched codeword comprising systematic bits and parity-check bits. Furthermore, the transmitting device jointly interleaves the systematic bits and parity-check bits of the rate-matched codeword to obtain an interleaved codeword. The systematic bits of the interleaved codeword are mapped to modulation label positions of a modulation constellation with first reliabilities, and the parity-check bits of the interleaved codeword are mapped to modulation label positions of the modulation constellation with second reliabilities.

A method includes applying, to a modulated digital signal, a forward error correction (FEC) including a low-density parity-check (LDPC) to produce a coded digital signal. Nyquist shaping is applied to the coded digital signal to generate a filtered digital signal. A representation of the filtered digital signal is transmitted in an optical communication channel via a dense wavelength division multiplexing (DWDM) scheme.

A system and a method are disclosed for processing data to be mapped into a transport block transmitted over a wireless physical shared channel. In one embodiment, a code block determination circuit determines a size of a code block of data that maps across at least one slot boundary of a slot of the wireless physical shared channel. A rate matching circuit rate matches bits of a code block to a number of bits available in the transport block that spans one or more slots of the wireless physical shared channel. An interleaver interleaves an output of the rate matching circuit so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved between the first slot and the second slot.