A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.

A subspace pursuit apparatus for compressive sensing reconstruction includes: a first inner product unit configured to calculate a correlation between a residual vector and column vectors of a sensing matrix by calculating an inner product of them; a first sorting unit coupled to the first inner product unit and configured to select K column vector indices having highest correlations, where K is a sparsity level; a second inner product unit configured to calculate a matrix for calculating a pseudo-inverse matrix required for solving a least-squares from the sensing matrix to store in the Gram matrix buffer; a Cholesky inversion unit configured to perform a Cholesky decomposition of the matrix stored in the Gram matrix buffer and calculate an inverse of a decomposed matrix; and a sparse solution estimator configured to estimate the sparse solution from a matrix value of the matrix based on the inverse of the decomposed matrix.

Systems, methods, and instrumentalities are described herein that may be used for reduced complexity polar encoding and decoding. There may be a set of encoding nodes to be used for polar encoding. An encoding node may be associated with a bit index and/or a relaxation level. A relaxation attribute may be selected for the encoding node. A relaxation group may be determined based on the relaxation attributes. The relaxation group may include two encoding nodes associated with consecutive bit indexes, an initial relaxation level, and the first relaxation attribute. A final relaxation level may be determined. Relaxation may be performed on the encoding nodes in the relaxation group. For example, an XOR operation between the encoding nodes may be omitted. Relaxation may be performed on the encoding nodes associated with each relaxation level up to the final relaxation level.

One example method includes obtaining L.sub.1 first decoding paths of an (i−1).sup.th group of to-be-decoded bits, where i is an integer, received data corresponds to P groups of to-be-decoded bits, and 1<i≤P, determining at least one second decoding path corresponding to each first decoding path, where a quantity of second decoding paths corresponding to each first decoding path is less than 2.sup.n, and where n is a quantity of information bits included in an i.sup.th group of to-be-decoded bits, and determining at least one reserved decoding path of the i.sup.th group of to-be-decoded bits in second decoding paths corresponding to the L.sub.1 first decoding paths. The at least one reserved decoding path includes a decoding result of the i.sup.th group of to-be-decoded bits.

A polar decoder circuit can execute successive cancellation list polar decoding on multiple threads concurrently. An LLR update engine of the polar decoder circuit and a sort engine of the polar decoder circuit can operate concurrently, with the LLR update engine computing updated path metrics for one codeword while the sort engine sorts candidates for one or more other codewords according to path metrics already computed by the LLR update engine. Threads corresponding to different codewords can cycle sequentially between the LLR update engine and the sort engine.

An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.

A decoder circuit includes first and second decoders. The first decoder is a first type of decoder configured to receive data encoded with an error correction code and decode and eliminate errors from a first subset of codewords of the data. The second decoder is a second type of decoder configured receive the data encoded with the error correction code and decode and eliminate errors from a second subset of codewords of the data, different from the first subset of the codewords, without attempting to decode and eliminate errors from the first subset of the codewords.

A storage which, in operation, stores a first minimum value and a second minimum value each time a plurality of data are input. Round-robin comparison circuitry which, in operation, makes a magnitude comparison among the plurality of data. First selection comparison circuitry and second selection comparison circuitry which, in operation, make a magnitude comparison between the first minimum value and each of the plurality of data and a magnitude comparison between the second minimum value and each of the plurality of data, respectively. Judgment circuitry which, in operation, judges a new first minimum value and a new second minimum value on the basis of a comparison result from the round-robin comparison circuitry and comparison results from the first and second selection comparison circuitry.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Certain aspects of the present disclosure relate to techniques and apparatus for enhanced decoding, for example, by providing a multi-phase tail biting convolutional code (TBCC) decoding algorithm. An exemplary method generally includes obtaining, via a wireless medium, a codeword encoded with a TBCC encoding scheme, generating metrics for candidate paths through trellis stages of a decoder, propagating information from at least one of the trellis stages to a later trellis stage, while generating the metrics, selecting a set of the candidate paths based on the propagated information, and decoding the encoded codeword by evaluating the selected set of candidate paths based, at least in part, on the generated metrics. Other aspects, embodiments, and features are claimed and described.