Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.

[Object] To provide a communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program that are capable of contributing to improving a radio communication technology related to IDMA. [Solution] Provided is a communication control apparatus including: a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

Techniques relating to LDPC encoding. A set of operations is produced that is usable to generate an encoded message based on an input message. The set of operations corresponds to operations for entries in a smaller matrix representation that specifies locations of non-zero entries in an LDPC encoding matrix. A mobile device is configured with the set of operations to perform LDPC encoding. Circuitry configured with the set of operations performs LDPC encoding with high performance, relatively small area and/or low power consumption.

The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method of a receiving apparatus in a communication system supporting a low density parity check (LDPC) code is provided. The method includes deactivating variable nodes of which absolute values of log likelihood ratio (LLR) values are greater than or equal to a first threshold value; changing LLR values of variable nodes of which absolute values of LLR values are less than a second threshold value among variable nodes other than the deactivated variable nodes to a preset value, and detecting LLR values of check nodes based on LLR values of the variable nodes other than the deactivated variable nodes.

Devices, systems and methods for convolutional precoding and decoding of polar codes are disclosed. An example method for error correction in a data processing system includes receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis, and performing, based on the trellis, a list-decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages.

According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.

A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

A hardware complexity reduction method for successive cancellation list decoders (SCL) is provided. In path pruning stages of an SCL decoding, L paths with smallest path metrics out of 2L candidate paths are chosen as surviving candidate paths as in a conventional SCL algorithm. Moreover, path indexes of L surviving candidate paths are provided in a sorted manner according to indexes at an output of a sorter module. After a path pruning, instead of L-to-1 multiplexers, (L/2+1)-to-1 multiplexers are deployed to perform copying operations of any required elements stored in dedicated registers of the L surviving candidate paths.

Embodiments include applying neural network technologies to encoding/decoding technologies by training and encoder model and a decoder model using a neural network. Neural network training is used to tune a neural network parameter for the encoder model and a neural network parameter for the decoder model that approximates an objective function. The common objective function may specify a minimized reconstruction error to be achieved by the encoder model and the decoder model when reconstructing (encoding then decoding) training data. The common objective function also specifies for the encoder and decoder models, a variable f representing static aspects of the training data and a set of variables z1:T representing dynamic aspects of the training data. During runtime, the trained encoder and decoder models are implemented by encoder and decoder machines to encode and decoder runtime sequences having a higher compression rate and a lower reconstruction error than in prior approaches.

Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.