Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix (G matrix) formed of a concatenation of a parity matrix (P matrix) and an identity matrix; determining a number of rows in the P matrix for a truncated P matrix in view of a correcting strength and a number of data bits; selecting a first subset of rows and a second subset of rows in the P matrix, wherein a first sum of row weights of each row in the first subset of rows is equal to or less than a second sum of row weights of each row in the second subset of rows; and generating the truncated P matrix by keeping the first subset of rows of the P matrix so as to minimize a number of logic gate operations.

Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.

A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.

An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

A coding method, a decoding method, an apparatus, and a device are provided. The method includes: coding, by a sending device, an information bit sequence to obtain a coded bit sequence, where the coded bit sequence includes an information bit, a frozen bit, a CRC check bit, and a frozen check bit; and a value of the frozen check bit and a value of the CRC check bit are obtained by using a same cyclic shift register; performing, by the sending device, polar coding and rate matching on the coded bit sequence to obtain a to-be-sent rate-matched sequence; and sending, by the sending device, the rate-matched sequence. According to the method, time and space for coding calculation and decoding calculation can be effectively reduced, and calculation complexity is reduced.

A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.

A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

A system is provided for performing erasure coding (EC) in a distributed storage system. During operation, the system can perform a partial encoding of a received first set of data fragments and second set of data fragments using EC to generate a first and a second EC codeword, respectively. The system can then distribute the first and the second set of data fragments among a set of storage nodes within the distributed storage system. The system can also distribute a first and the second set of intermediate parity fragments in the first and second EC codeword, respectively, among a subset of the storage nodes with alignments. The system can then merge the first and the second set of intermediate parity fragments to generate an overall parity for both the first and the second set of data fragments. The system can store, based on the alignments, each overall parity fragment in the overall parity in the corresponding subset of storage nodes.