Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.

An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w.box-tangle-solidup.) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w.box-tangle-solidup.) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=┌n/w.box-tangle-solidup. clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.

A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.

According to some embodiments, a method in a wireless transmitter comprises: receiving a plurality of bits for a wireless transmission; determining a maximum code block size for the transmission based on code rate, maximum code word size Nmax, and design parameters of the channel code; segmenting the plurality of bits into one or more code block segments such that no one of the one or more code block segments is larger than the determined maximum code block size; and transmitting the one or more code block segments to a wireless receiver. In particular embodiments, the design parameters of the channel code limit the maximum code block size to Kmax for any code rate. The determined maximum code block size may be limited by code rate and Nmax such that the maximum code block size does not exceed code rate times Nmax.

According to some embodiments, a method in a wireless transmitter of aligning code blocks with modulation symbols comprises: receiving a block of information bits for wireless transmission in a plurality of modulation symbols; partitioning the plurality of modulation symbols into groups of one or more modulation symbols, wherein the modulation symbols in a group are contiguous in time; and assigning each of the information bits to one of the groups. For each of the groups the method further comprises: segmenting the assigned information bits in the group into one or more code blocks; encoding each code block into coded bits; and assigning the coded bits of the one or more code blocks to the group of modulation symbols the information bits are assigned to. The method further comprises transmitting the groups of modulation symbols to a wireless receiver.

Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.

A turbo encoding method includes obtaining a code block for turbo encoding, storing a data block of the code block in a plurality of parallel caches, and obtaining parallel data from the plurality of parallel caches for turbo encoding.

The code block segmentation method includes: a base station determining whether to use the maximum length of a first pre-set information bit for code block segmentation or to use the maximum length of a second pre-set information bit for code block segmentation; if it is determined to use the maximum length of the first pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the first pre-set information bit as an upper limit; and if it is determined to use the maximum length of the second pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the second pre-set information bit as an upper limit, wherein the maximum length of the first pre-set information bit is greater than the maximum length of the second pre-set information bit.