An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=n/w) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=n/w) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=n/w clock cycle; where the bit pattern vector comprises n bits, of which k bits adopt a first binary value and nk bits adopt a complementary binary value.

An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

A computer-implemented method for error-correction-encoding and encrypting of a file is provided. The file is split into at least two blocks. The first block is encrypted using a given encryption key. The encrypted first block is encoded twice using a first and second forward error correction code of the first block. Each subsequent block is encrypted by performing an algebraic operation. The encrypted block is encoded twice using a first and second forward error correction code for this block, wherein a cryptographic indexing function provides a set of indices used by the second forward error correction code to produce the second encoded chunk. The first encoded chunks of each encrypted block are outputted. The computer-implemented method enables secure transmission of a file content between low power devices.

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

The code block segmentation method includes: a base station determining whether to use the maximum length of a first pre-set information bit for code block segmentation or to use the maximum length of a second pre-set information bit for code block segmentation; if it is determined to use the maximum length of the first pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the first pre-set information bit as an upper limit; and if it is determined to use the maximum length of the second pre-set information bit for code block segmentation, the base station segmenting a transport block into one or more segments by taking the maximum length of the second pre-set information bit as an upper limit, wherein the maximum length of the first pre-set information bit is greater than the maximum length of the second pre-set information bit.

In order provide a communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program that are capable of contributing to improving a radio communication technology related to IDMA, a communication control apparatus is provided. The communication control apparatus includes a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a list decode circuit may include a syndrome calculation circuit, a symbol erasure circuit, an erasure syndrome calculation circuit and a Berlekamp-Massey algorithm circuit (BMA), and an error locator polynomial (ELP) evaluation circuit. The syndrome calculation circuit may calculate a baseline syndrome and erasure syndrome calculation circuit may calculate erasure syndromes from error locator polynomials calculated by the symbol erasure circuit. The BMA circuit may use the calculated syndromes to generate a series of ELPs, which may be used by the ELP evaluation circuit to identify error locations in a codeword.

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Method and apparatus for interleaving is provided. The method includes the following steps: constructing a plurality of pseudorandom sequences according to a pre-defined length of an interleaving sequence to be constructed; for each of the constructed pseudorandom sequences, constructing at least one corresponding numerical digit random sequence according to a number of more than two types of numerical values in this pseudorandom sequence; and, for each of the constructed pseudorandom sequences and the at least one corresponding numerical digit random sequence thereof, constructing a corresponding interleaving sequence according to a mapping relation between this pseudorandom sequence and the numerical digit random sequence, so that a plurality of interleaving sequences are allocated and indicated as multiple access signatures.

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.