There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into FN/M folding sections, each of the constellation words being associated with one of the FN/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Methods and apparatus for operating a communication system comprising three or more communication transceivers. In illustrative embodiments, multiple different cyclic redundancy check (CRC) generation schemes are maintained. Each CRC generation scheme corresponds to a unique CRC residual value. A CRC value generated using one of the CRC generation schemes is placed in a data packet to be transmitted. The chosen CRC generation scheme reflects which one or more transceivers are intended recipients of the data packet. When a data packet is received by a transceiver, a CRC residual value is calculated based on the CRC value contained in the received data packet. The calculated CRC residual value is compared against a list of one or more valid CRC residual values for that particular transceiver. If the calculated CRC value matches one of the listed valid CRC residual values, the data packet is accepted, otherwise it is rejected.

A plurality of units have a transmitter and a receiver. The transmitter puts the unit's own data string into a coding data array using first array information, and calculates an error-correcting code based on the data array in which 0 is put except for the data string. The receiver decodes a data array in which a data string is put into the coding data array based on second array information, using an error-correcting code. The transmitter adds the unit's own data string to a data string, puts the unit's own data string into the coding data array using the first array information on the data string, calculates an error-correcting code for the data array in which 0 is put except for the data string, and determines an error-correcting code of a transmission packet by addition of an error-correcting code of a received packet and the calculated error-correcting code.

A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises MN sub-matrices, wherein each of the sub-matrices is a ZZ matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

In order provide a communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program that are capable of contributing to improving a radio communication technology related to IDMA, a communication control apparatus is provided. The communication control apparatus includes a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.