Generally discussed herein are systems, devices, and methods for entwined encryption and error correction and/or error detection. An entwined cryptographic encode device can include a memory including data indicating a set of relatively prime, irreducible polynomials stored and indexed thereon, entwined encryption encoding circuitry to receive data, transform the data to a set of data integers modulo respective polynomial integers representative of respective polynomials of the polynomials stored on the memory, and perform a Da Yen weave on the transformed data based on received cipher data, and provide the weaved transformed data to a medium.

A packet transmission/reception apparatus and method is provided. The packet transmission method of the present invention includes acquiring a source payload including partial source symbols from a source block, generating a source packet including the source payload and an identifier (ID) of the source payload, generating a repair packet including a repair payload corresponding to the source payload and an ID of the repair payload, generating a Forward Error Correction (FEC) packet block including the source and repair packets, and transmitting the FEC packet block. The source payload ID includes a source payload sequence number incrementing by 1 per source packet. The packet transmission/reception method of the present invention is advantageous in improving error correction capability and network resource utilization efficiency.

A receiver receives a signal including an interleaved symbol stream. The receiver includes a convolutional deinterleaver including a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector inputs the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

A method and apparatus for transmitting and receiving a Relay Physical Downlink Control Channel (R-PDCCH) being a control channel for a relay node (RN) in a wireless communication system are disclosed. To transmit an R-PDCCH to a RN, a BS includes a processor for interleaving a predetermined number of Control Channel Elements (CCEs), mapping the interleaved CCEs to at least one Virtual Resource Block (VRB) configured for R-PDCCH transmission, mapping the at least one VRB to at least one Physical Resource Block (PRB), and a transmitter for transmitting the R-PDCCH to the RN through the at least one PRB.

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.

A communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program capable of contributing to improving a radio communication technology related to IDMA. The communication control apparatus including: a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

Systems and methods for processing a multitude of variable and varying signals in real time with low latency using fixed hardware with fixed processing resources, such as those within an application-specific integrated circuit (ASIC) or a field-programmable gated array (FPGA). The signal processing systems and methods allow the resource allocation to continuously adjust their processing as a result of changing signal conditions. In accordance with various embodiments, fixed processing resources in ASIC or FPGA form are dynamically allocated through an intelligent interleaving methodology that efficiently maps the signal processing of incoming signals while essentially preserving the same latency as if each signal channel were processed at the full sample rate. This is accomplished by multiplexing under the control of a resource sharing algorithm.

A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (32.sub.1, 32.sub.2) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL.sub.1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (32.sub.1, 32.sub.2) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL.sub.1) or the two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2).

A decoding method and a decoder for a low-density parity-check (LDPC) code, where the method includes dividing, by a decoder, an LDPC code C whose bit length is n into k LDPC codes D={D.sub.1,D.sub.2,K, D.sub.k-1, D.sub.k}, arranging, by the decoder, D.sub.i, i=1, 2, K, k1, k by column to obtain transpose codes D.sup.T={D.sub.1.sup.T,D.sub.2.sup.T,K, D.sub.k-1.sup.T, D.sub.k.sup.T} of the LDPC codes D, performing cyclic shift on D.sub.i.sup.T, i=1, 2, K, k1, k by row according to values of corresponding elements in a target check matrix to obtain shift codes E={E.sub.1,E.sub.2,K,E.sub.t-1,E.sub.t}, where t is equal to a quantity of rows of the target check matrix, obtaining, by the decoder, t*m groups of LDPC subcodes F.sub.1, F.sub.2,K, F.sub.tm-1, F.sub.tm according to the shift codes E and a bit length d of the decoder, where E.sub.j is divided into groups, E.sub.j={(E.sub.j).sub.1.sup.d,(E.sub.j).sub.d+1.sup.2d,K,(E.sub.j).sub.(m-2)d+1.sup.(m-1)d,(E.sub.j).sub.(m-1)d+1.sup.md}={F.sub.(j-1)m+1,F.sub.(j-1)m+1,K,F.sub.jm-1,F.sub.jm}, and m=l/d, and decoding, by the decoder, the m groups of LDPC subcodes to obtain a decoding result of the LDPC code C.