A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block.

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.

Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.

A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.

A method includes receiving a time domain resource allocation (TDRA) list configuration including entries, each including a resource allocation that includes a slot offset value. L1 signaling is received indicating a minimum slot offset value. Downlink control information (DCI) is decoded on a physical downlink control channel in a slot. An index is obtained from the decoded DCI, identifying an entry in the TDRA list. A particular slot offset value identified by the index is retrieved from the TDRA list and compared with the minimum slot offset value. If the particular slot offset value is less than the minimum slot offset value, the entry is invalid. If the particular slot offset value is greater than or equal to the minimum slot offset value, a physical downlink shared channel is received.

In a coding device (20), a first coding unit (21) generates a parity of an RS code by coding, based on the RS code, each first data sequence existing in a direction different from a row direction of input data, and generates coded data by attaching the parity of the RS code to each first data sequence, thereby consequently expanding a matrix. A second coding unit (22) generates a parity of a BCH code and a parity of an LDPC code by coding, based on the BCH code and the LDPC code, each second data sequence existing in a row direction of the coded data, and generates a plurality of DVB-S2 frames (13) including, per DVB-S2 frame (13), one data sequence existing in the row direction of the coded data, the corresponding parity of the BCH code, and the corresponding parity of the LDPC code.

A network node having a receiver for receiving input packets, a local node memory where one or more parameters for coding are stored, an encoder for creating coded packets from the input packets using linear network coding, and a transmitter to transmit the coded packets. Each coefficient of the linear network coding is a parameter of the one or more parameters or a pre-determined function of the one or more parameters. A related method and a network are also presented.

According to some embodiments, a method in a wireless transmitter comprises: receiving a plurality of bits for a wireless transmission; determining a maximum code block size for the transmission based on code rate, maximum code word size Nmax, and design parameters of the channel code; segmenting the plurality of bits into one or more code block segments such that no one of the one or more code block segments is larger than the determined maximum code block size; and transmitting the one or more code block segments to a wireless receiver. In particular embodiments, the design parameters of the channel code limit the maximum code block size to Kmax for any code rate. The determined maximum code block size may be limited by code rate and Nmax such that the maximum code block size does not exceed code rate times Nmax.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.