A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.

A method of configuring an error correction engine, the method comprising determining the frequency of operation of the error correction engine, determining the size of the code to be error corrected, determining the time permitted in which to error correct the code, and based on the determining steps, configuring the number of active error correction processes within the error correction engine to be used to error correct the code.

A system and method for probabilistic shaping of an eight-dimensional super-symbol in optical transport networks, including receiving binary data to be transmitted as an optical signal; mapping at least a portion of the binary data to symbols of a M-QAM constellation; generating a first four-dimensional symbol of the M-QAM constellation for a first symbol period, including applying probabilistic shaping to the first four-dimensional symbol; generating a second four-dimensional symbol of the M-QAM constellation for a second symbol period, the second symbol period consecutive to the first symbol period, wherein the first and the second four-dimensional symbols have i) an equal symbol energy and ii) a one-to-one relationship; and time interleaving the first symbol period and the second symbol period to generate an eight-dimensional super-symbol.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes obtaining a payload to be transmitted, partitioning the payload into a plurality of payload sections, deriving redundancy check information for each respective payload section of the plurality of payload sections, merging the redundancy check information for each payload section with the plurality of payload sections to form a sequence of bits, and generating a codeword by encoding the sequence of bits using an encoder. Other aspects, embodiments, and features are also claimed and described.

Flexible Ethernet (FlexE) Forward Error Correction (FEC) systems and methods include mapping a first set of calendar slots including Ethernet payload clients to a FlexE Time Division Multiplexing (TDM) structure including a plurality of calendar slots; and mapping a second set of calendar slots including FEC data to the FlexE TDM structure, wherein the first set of calendar slots and the second set of calendar slots fill the FlexE TDM structure. In an exemplary embodiment, an overall Physical (PHY) rate of the FlexE TDM structure is kept constant with a reduction in bandwidth for the Ethernet payload clients based on the second set. In another exemplary embodiment, the overall Physical (PHY) rate of the FlexE TDM structure is increased based on the second set of calendar slots, to support a set rate for the Ethernet payload clients with a reduced number of calendar slots.