A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block.

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a check part of the LDPC codeword to obtain a check bit stream; splicing an information bit part of the codeword and the check bit stream into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving; and performing constellation mapping on the codeword after the third bit interleaving according to a constellation diagram to obtain a symbol stream; the permutation orders (bit-swapping patterns) and the constellation diagrams used in the interleaving and mapping processing of LDPC codes with different code rates, code length and LDPC code tables are designed and optimized using theoretical analysis. The technical solution reduces the receiving threshold of the receiving end.

Communication endpoints and related methods for forward error correction (FEC) are disclosed. A communication endpoint includes control circuitry including a packetizer configured to segment near-end data into groups of near-end data packets, and a forward error correction (FEC) packet generator configured to generate at least two near-end FEC packets for each group of near-end data packets. A method includes generating the FEC packets, and transmitting the data packets and the FEC packets to a far-end communication endpoint. A communication endpoint includes control circuitry including a forward error correction repairer configured to use far-end FEC packets to repair groups of far-end data packets. A method includes receiving a group of far-end data packets and corresponding far-end FEC packets, and repairing far-end data packets with the corresponding far-end FEC packets.

Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.

Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.

A method of configuring an error correction engine, the method comprising determining the frequency of operation of the error correction engine, determining the size of the code to be error corrected, determining the time permitted in which to error correct the code, and based on the determining steps, configuring the number of active error correction processes within the error correction engine to be used to error correct the code

Flexible Ethernet (FlexE) Forward Error Correction (FEC) systems and methods include mapping a first set of calendar slots including Ethernet payload clients to a FlexE Time Division Multiplexing (TDM) structure including a plurality of calendar slots; and mapping a second set of calendar slots including FEC data to the FlexE TDM structure, wherein the first set of calendar slots and the second set of calendar slots fill the FlexE TDM structure. In an exemplary embodiment, an overall Physical (PHY) rate of the FlexE TDM structure is kept constant with a reduction in bandwidth for the Ethernet payload clients based on the second set. In another exemplary embodiment, the overall Physical (PHY) rate of the FlexE TDM structure is increased based on the second set of calendar slots, to support a set rate for the Ethernet payload clients with a reduced number of calendar slots.

A coding method with differentiated protection to protect, with a different protection efficiency, a number of groups of data in a frame to be transmitted. The invention is based for that on the use of a correcting code of the LDPC type concatenated with an algebraic correcting code. The invention also proposes a decoding method compatible with the coding method with differentiated protection.

An apparatus and method are described. The apparatus includes a transceiver and processor, which attach transport block (TB) level CRC bits to a TB, select an LDPC base graph (BG) based on a code rate (CR) and TB size of the TB including TB level CRC bits, determine a number of code blocks (CBs) to use for segmenting the TB including TB level CRC bits depending on the selected LDPC BG, determine a single CB size for each of the CBs based on the number of CBs, segment the TB including TB level CRC bits into the CBs based on the number of CBs and CB size, pad zeros to a last CB of the CBs in the segmented TB, attach CB level CRC bits to each CB in the segmented TB, encode each CB in the segmented TB using the selected LDPC base graph, and transmit the encoded CBs.

Provided is a CRC calculation circuit capable of dealing with various types of generator polynomials with a simple configuration. A CRC calculation circuit (100) includes a generator polynomial register (110) configured to store polynomial data, and a plurality of CRC calculation units (120) connected in series and provided so as to correspond to the number of bits of input data. The CRC calculation units (120) each include a barrel shifter (121) configured to shift calculated data by one bit using the input data or output data from a pre-stage CRC calculation unit as the calculated data; an XOR circuit (122) configured to perform XOR calculation of the shifted data and the polynomial data; and a multiplexer (123) configured to select, based on the calculated data, the shifted data or calculation result data.