This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages. The sub-decoders are configured to operate concurrently for simultaneously decoding individual sub-codes.

A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

A Polar code decoding method and apparatus, a storage medium, and a terminal are provided. The method includes: dividing a Polar code having a length of N into S groups of Polar codes, each group of the S groups of Polar codes being data extracted from the Polar code having the length of N according to a preset rule, and S being an integer power of 2; and performing joint decoding on calculation results of the S groups of Polar codes after performing a logarithm likelihood ratio (LLR) calculation on each group of the S groups of Polar codes.

Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel designs. In a particular embodiment, a method includes, in a data storage device including a controller and a non-volatile memory, the controller includes an inverse Fourier transform circuit having a first number of inputs coupled to multipliers, receiving elements of an input vector and providing the elements to the multipliers. The multipliers are configured to perform calculations associated with an inverse Fourier transform operation. The first number is less than a number of inverse Fourier transform results corresponding to the inverse Fourier transform operation.

An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.

Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

Techniques relating to LDPC encoding. A set of operations is produced that is usable to generate an encoded message based on an input message. The set of operations corresponds to operations for entries in a smaller matrix representation that specifies locations of non-zero entries in an LDPC encoding matrix. A mobile device is configured with the set of operations to perform LDPC encoding. Circuitry configured with the set of operations performs LDPC encoding with high performance, relatively small area and/or low power consumption.

Disclosed relates to a decoder for LDPC code, including: a variable node processing unit; a check node processing unit; a memory for storing iterative messages of edges of a parity-check matrix for LDPC code; and a controller for controlling the node processing units to perform iterations of decoding until the decoding ends, wherein, in each iteration of decoding, the controller controls the variable node processing unit to compute variable node messages in a traversing manner for all variable nodes and updates the iterative messages in the memory according to the computed variable node messages, and controls the check node processing unit to compute check node messages in a traversing manner for all check nodes and updates the iterative messages in the memory according to the computed check node messages.