A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.

An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (32.sub.1, 32.sub.2) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL.sub.1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (32.sub.1, 32.sub.2) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL.sub.1) or the two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2).

Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.

Systems and methods are provided for decoding a codeword using an iterative decoding process. The systems and methods include receiving a codeword comprising a plurality of symbols, and concurrently processing the received codeword with a detector and a decoder based in part on extrinsic information associated with the plurality of symbols to obtain updated extrinsic information. The systems and methods further include modifying the extrinsic information associated with the plurality of symbols based on the updated extrinsic information, and repeating the processing and modifying steps until a stopping criterion is met.

An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (32.sub.1, 32.sub.2) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL.sub.1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (32.sub.1, 32.sub.2) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL.sub.1) or the two series of yet-to-be-coded bit sequences (IL.sub.1, IL.sub.2).

Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.

Herein provided are methods and systems for decoding polar codes. A data flow graph relating to a predetermined polar code is converted to a tree graph comprising rate-zero nodes, rate-1 nodes, and rate-R nodes. A rate-R node within the binary tree is replaced with a maximum likelihood node when predetermined conditions are met thereby replacing a sub-tree of the tree graph with a single maximum likelihood node.

A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.

Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.