Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where PP.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.

A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises MN sub-matrices, wherein each of the sub-matrices is a ZZ matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.

A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage. The interconnection network is operable to route, on the basis of routing commands applied to the switching elements, N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals. Additionally, M denotes a number of given submultiples of N whose product is equal to N. Each stage is associated with a respective submultiple of said M given submultiples of N, and includes S.sub.i switching elements, each having sm.sub.i respective input pins and sm.sub.i respective output pins, wherein S.sub.i=N/sm.sub.i, wherein sm.sub.i denotes the respective submultiple associated with the stage, and wherein i denotes the stage and is a positive integer comprised between one and M.

Systems and methods for accommodating variable page sizes in solid-state drives using customized error correction are disclosed. In one embodiment, a system is disclosed comprising a NAND Flash storage device comprising a plurality of NAND Flash pages; a NAND FTL configured to convert a LBA of a NAND Flash page to a PBA; a syndrome calculator configured to calculate a syndrome using a LBA and an LBA parity matrix, the LBA associated with a read command issued by a host device; and an ECC decoder configured to: read a codeword located at a PBA associated with the LBA associated with the read command, the codeword including a plurality of user data bits and a plurality of parity bits, confirm that the codeword does not contain an error if the codeword converges with the syndrome, and transmit the user data bits to the host device as a response to the read command.