Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.

A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.

In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

A method for sending a secure message within a dispersed storage network (DSN). The method begins with a source computing device sending a notice of a write communication operation to a destination computing device regarding the secure message and sending a set of write communication requests to a set of storage units, wherein the secure message is dispersed storage error encoded into a set of encoded data slices. The method continues by at least some storage units storing at least some encoded data slices in a communication vault. The method continues with the destination computing device sending at least a decode threshold number of write commit communication requests to at least a decode threshold number of storage units of the at some storage units. The method continues by the at least the decode threshold number of storage units sending encoded data slices to the destination computing device.

According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.

Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.

Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.