An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a k-bit original data in parallel and configured to perform a plurality of XOR operations to the k-bit original data to output a (nk)-bit parity data. The k-bit original data and the (nk)-bit parity data form an n-bit codeword, k denotes a natural number and n denotes a natural number which is greater than k.

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.

A computer-implemented method includes encoding an array of (p1)k symbols of data into a p(k+r) array. The method includes p is a prime number, r1, and kpr. The method also includes each column in the p(k+r) array has an even parity and each line of slope j for 0jr1 in the p(k+r) array has an even parity. The method includes the lines of slope j taken with a toroidal topology modulo p. A computer program product for encoding an array of (p1)k symbols of data into a p(k+r) array includes a computer readable storage medium having program instructions executable by a computer. The program instructions cause the computer to perform the foregoing method.

Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=n/w) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=n/w) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=n/w clock cycle; where the bit pattern vector comprises n bits, of which k bits adopt a first binary value and nk bits adopt a complementary binary value.

Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

With CRC-code-computation logic used in electronic-communications hardware, many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. A component-efficient CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.