Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

The current document is directed to component-efficient CRC-code-computation logic used in electronic-communications hardware. Many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. The currently disclosed CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.

A method of encoding input data. The method includes receiving a plurality of data bits of a bit stream. The method further includes forming words using the plurality of data bits to create a plurality of data packets including a first data packet. The method further includes encoding the words of the first data packet into coded words, partitioning the coded words into a plurality of blocks of M words each and integrating the coded words in each block in an interleaved order to generate a coded data packet for transmission through a communication channel.

A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.

This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.

Embodiments of this application disclose a method includes: An encoder side obtains a plurality of data blocks in batches, and encodes the plurality of data blocks. In an i.sup.th time of encoding, after obtaining an incremental data block, the encoder side performs encoding processing on the incremental data block by using erasure code to generate an incremental parity block, the incremental data block includes at least one data block, and i is an integer greater than 1. The encoder side performs an exclusive OR operation based on the incremental parity block and an original global parity block to generate a first incremental global parity block. The original global parity block is a first incremental global parity block generated by the encoder side in an (i?1).sup.th time of encoding, and an original data block is a data block obtained by the encoder side before the (i?1).sup.th time of encoding.

An erroneous bit determining circuit and a method are provided. The method includes: respectively performing a Hamming operation for an information symbol having an even weight and an information symbol having an odd weight to acquire a check symbol configured for the information symbol having an even weight and a check symbol configured for the information symbol having an odd weight; and respectively generating corresponding code words based on the information symbol having an even weight, the information symbol having an odd weight and the check symbols configured therefor. In this way, information symbols having the same number of bits are corrected without increasing the number of check symbol bits, and thus symbol transmission rate is improved.

An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.