In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

A parity check circuit may include a first signal combination unit for generating first to N.sup.th combination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.th combination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.th signals, a parity check unit for detecting whether an error is present in the first to N.sup.th signals in response to the N.sup.th combination signal, a second signal combination unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.th reconstruction signal of the first to N.sup.th reconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.th combination signals, and a signal storage unit for storing the first to N.sup.th reconstruction signals.

In an encoding method, data segments and encoding information which indicates encoding patterns each representing a set of data segments used for a predetermined encoding calculation are acquired. An encoded data piece is generated by performing the predetermined encoding calculation based on each encoding pattern, and is stored in the memory. A first encoding pattern for generating the encoded data piece is compared to a second encoding pattern for a next encoding calculation, and the next encoding calculation is performed by using the encoded data piece corresponding to the first encoding pattern when at least a part of the second pattern is common with the first encoding pattern.

Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.

A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

A parity check circuit may include a first signal combination unit for generating first to N.sup.thcombination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.thcombination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.thsignals, a parity check unit for detecting whether an error is present in the first to N.sup.thsignals in response to the N.sup.th combination signal, a second signal combination iO unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.threconstruction signal of the first to N.sup.threconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.thcombination signals, and a signal storage unit for storing the first to N.sup.threconstruction signals.

Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.

In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.