A data processing system having a neural network architecture for receiving a binary network input and, in dependence on the binary network input, propagating signals via a plurality of processing nodes, in accordance with respective binary weights, to form a network output, the data processing system being configured to train a node by implementing an error correcting function to identify a set of binary weights which minimize, for a given input to the node, any error between an output of the node when formed in accordance with current binary weights of the node and a preferred output from the node and to update the binary weights of the node to be the identified weights. This training is performed without storing and/or using any higher arithmetic precision weights or other components.

Provided herein are methods and systems for applying an ensemble comprising a plurality of neural network based decoders trained using actively selected training samples for decoding error correction encoded codewords which are also encoded for error detection before transmitted over transmission channels subject to interference. In particular, each of the neural network based decoders is associated with only a limited size region of the distribution space of the error correction code where the distribution space is partitioned based on error detection values computed for the encoded codewords. As such each of the decoders is specialized for decoding encoded codewords mapped to its limited size associated region. During run-time a received encoded codeword may be mapped to one of the regions and may be fed accordingly to one of the neural network based decoders of the ensemble which is associated with the mapped region.

A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

A reliable data transmission method and system based on a predicted amount of data in a vehicle-to-infrastructure (V2I) network is disclosed. A data transmission method of a base station includes determining a maximum amount of data to be transmitted from the base station disposed around a road to a vehicle traveling on the road, determining an encoding number for systematic network coding (SNC) based on the determined amount of data, performing the SNC on original data based on the encoding number and the amount of data, and transmitting encoded data obtained by performing the SNC to the vehicle.

A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

A method of telecommunications includes the steps of receiving an encoded block having a plurality of values, dividing the received encoded block into a plurality of received segments, each received segment comprising at least two of the values, decoding each received segment by providing, for each received segment, a plurality of estimated encoded sequences, each estimated encoded sequence comprising at least two data units, merging estimated encoded sequences for consecutive segments to provide a plurality of candidate sequences, and selecting one of the plurality of candidate sequences by performing a closest fit calculation between the received encoded data block and each of the candidate sequences. The method is suitable for use in software-defined radios.

An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

A decoding method includes: decoding first to-be-decoded information based on a first decoder to obtain a first decoding result that includes first soft information or a first hard output; and correcting the first decoding result based on a first correction model to obtain a corrected first decoding result of the first to-be-decoded information. The first correction model is obtained through training based on training data that includes a training decoding result and a corrected training decoding result. The training decoding result is a decoding result obtained after the first decoder decodes training to-be-decoded information, and the corrected training decoding result is a corrected decoding result corresponding to the training decoding result. In this way, after a decoder performs decoding, a decoding result can be corrected based on a correction model.

A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.