Examples described herein utilize multi-layer neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing the neural network decoders. In this manner, neural networks described herein may be used to implement error code correction (ECC) decoders.

A system for reducing analog noise in a noisy channel, comprising: an interface configured to receive analog channel output comprising a stream of noisy binary codewords of a linear code; and a computation component configured to perform the following: for each analog segment of the analog channel output of block length: calculating an absolute value representation and a sign representation of a respective analog segment, calculating a multiplication of a binary representation of the sign representation with a parity matrix of the linear code, inputting the absolute value representation and the outcome of the multiplication into a neural network for acquiring a neural network output, and estimating a binary codeword by component-wise multiplication of the neural network output and the sign representation.

A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.

Systems and methods are disclosed for decoding data. A first block of data may be obtained from a storage medium or received from a computing device. The first block of data includes a first codeword generated based on an error correction code. A first set of likelihood values is obtained from a neural network. The first set of likelihood values indicates probabilities that the first codeword will be decoded into one of a plurality of decoded values. A second set of likelihood values is obtained from a decoder based on the first block of data. The second set of likelihood values indicates probabilities that the first codeword will be decoded into one of the plurality of decoded values. The first codeword is decoded to obtain a decoded value based on the first set of likelihood values and the second set of likelihood values.

An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.

Systems and methods herein provide for error correction via Low Density Parity Check (LDPC) coding. In one embodiment, a system includes a data buffer operable to receive a block of Low Density Parity Check (LDPC) encoded data. The system also includes a processor operable to reduce a belief propagation algorithm used to encode the LDPC encoded data into a quadratic polynomial, to embed the quadratic polynomial onto a plurality of quantum bits (qubits), and to decode the block of LDPC encoded data via the qubits.

Message faulting is a critical unsolved problem for 5G and 6G. Disclosed herein is a method for combining an AI-based analysis of the waveform data of each message element, plus the constraint of an associated error-detection code (such as a CRC or parity construct of the correct message) to localize and, in many cases, correct a limited number of faults per message, without a retransmission. For example, the waveform data may include a deviation of the amplitude or phase of a particular message element, relative to an average of the amplitudes or phases of the other message elements that have the same demodulation value. The outliers are thereby exposed as the most likely faulted message elements. In addition, using the error-detection code, the AI model can determine the most likely corrected message, thereby avoiding retransmission delays and power usage and other costs.

Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements low-density parity-check (LDPC) decoding that uses bit flipping. In a decoding iteration, a feature map is generated for a bit of an LDPC codeword. The bit corresponds to a variable node. The feature map is input to a neural network that is trained to determine whether bits should be flipped based on corresponding feature maps. An output of the neural network is accessed. The output indicates that the bit should be flipped based on the feature map. The bit is flipped in the decoding iteration based on the output of the neural network.

Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.

An electronic device and an operating method of an electronic device are provided. The operating method includes configuring a self-correction condition for adjusting an information deletion and dropout rate, performing iterative decoding on the received information using decoding factors and a self-correction technique, determining whether decoding of the codeword succeeds or fails, based on a result of the decoding, storing a received signal and the codeword which are successfully decoded, based on a determination result, and optimizing the decoding factors, based on the stored received signal and codeword.