A device comprises a memory that stores instructions executed by one or more processors to obtain a plurality of received signals transmitted by a user equipment from a plurality of antenna elements in a cellular network. A plurality of complex channel values are calculated in an angle domain for a horizontal arrival angle and a vertical arrival angle per a received ray in a plurality of received rays in response to the plurality of received signals. A frequency-offset estimation is calculated and applied to the plurality of complex channel values. The plurality of offset complex channel values are transformed to a plurality of channel values in a time domain. A time-offset estimation is calculated and applied to the plurality of channel values. An expected value of the plurality of channel values is obtained to obtain a power angle delay profile for the geographical location of the user equipment.

Nyquist folding receivers (NYFRs) are disclosed that use three or more non-modulated sampling clock signals with different frequencies to produce multiple projections in a sampled output. Using these three or more different sampling clock signals, multiple Nyquist zones are aliased together while still allowing signals from different Nyquist zones to be separated and identified in later processing based upon the sampling provided by the different sampling clock signals. NYFR sampling receivers are also disclosed that simultaneously produce multiple separate and different parallel channels from an input signal, with each different channel having a different sampling clock sampling rate from the other channels so as to generate a respective folding pattern that is different from the folding pattern generated by the respective RF sampling rate of each of the other simultaneous and parallel channels. A particular signal may be separated and identified by matching it to the respective different folding patterns in each of the simultaneous multiple different parallel channels.

Embodiments of the present disclosure disclose a wireless transceiver. The wireless transceiver includes a second control switch, and the second control switch may selectively connect a signal output end of a coupler or a signal output end of a low noise amplifier LNA to a signal input end of the down converter. Therefore, when the signal output end of the coupler is connected to the down converter, the coupler, the down converter, and the analog-to-digital converter ADC form an observer; when the second control switch connects the signal output end of the low noise amplifier LNA to the signal input end of the down converter, a transceiver antenna, the low noise amplifier LNA, the down converter, and the analog-to-digital converter ADC form a receiver. Therefore, the embodiments of the present disclosure can greatly save hardware costs of a system for implementing an observer circuit.

The present disclosure discloses a method for adjusting one or more LO frequencies in a receiver. The receiver performs down conversion on a received signal through one or more mixers by using the one or more LO frequencies, and outputs one or more symbols through an ADC. The method comprising the steps of: for each of the one or more LO frequencies, estimating a new LO frequency corresponding to a best signal quality of the received signal; and adjusting the LO frequency into the new LO frequency. The present disclosure also relates to a receiver for adjusting one or more LO frequencies.

Provided is a method for, upon transmission of a DSC message being instructed, enabling quick start of the transmission. The method includes; (1) instructing, upon transmission of the DSC message being instructed, an antenna tuner to start tuning regardless of whether being busy or not, and switching an antenna from reception to transmission after the tuning is completed, (2) performing busy check, and standing by for a time period defined in the standard, when a reception signal in a transmission channel is no longer a dot pattern, and executing these processes (1) and (2) in parallel.

According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, n.sup.th order resonant bandpass filtering with n>1, and signal sub-sampling in an i.sup.th Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using n.sup.th order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Methods and systems in accordance with the present invention provide an RF spectrum analyzer on a computer chip, such as an integrated circuit. They may provide RF spectrum analyzer functions on a much smaller scale, which is easier to implement, transport and install in other equipment. They present a single chip solution that is smaller, lighter and more compact than conventional systems. Additionally, they may be put in hand held (or smaller) devices.

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by r.sub.i bit positions for the i-th second digital control code, wherein r.sub.i is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

A selective filtering module is arranged to filter or process the digital baseband signal consistent with a target receiving bandwidth, where the selective filtering module comprises a narrowband rejection filter and wide-band filter configured to reject an interference component that interferes with the received radio frequency signal. The narrowband rejection filter is configured to reject a first interference component, where the narrowband rejection filter comprises an adaptive notch filter (NF). The wide band rejection filter is configured to reject a second interference component in accordance with a pulse blanking technique. An electronic data processor is adapted to control one or more filter coefficients of narrowband rejection filter and the wide band rejection filter in accordance with one or more strategic filter control factors among ADC saturation, activation/deactivation of the notch filter, and a wide-band spectrum analysis.