H04B1/0007

System and method for signal interference rejection using human body communication
11374602 · 2022-06-28 · ·

A communication interference rejection system comprising a receiver operatively connected to a device connected to a body of a user. The receiver is configured to receive a signal transmitted through the body of the user, the signal comprising a data component and an interference component, the interference component due to human body antenna effect. The receiver is configured to integrate the signal using a relatively low-gain analog integrator and then digitally differentiate the output of said integration.

Device and method for receiving data in a radio frequency transmission
11374597 · 2022-06-28 · ·

According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.

Interleaving ADC error correction methods for Ethernet PHY

A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

SYSTEM COMPRISING MULTIPLE UNITS

A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.

Radio wave state analysis method
11362745 · 2022-06-14 · ·

A radio wave state analysis method acquires a radio wave for a place at which an audio system is sited, where the audio system includes one or more receiving devices for wireless reception of an audio signal; and generates relationship information indicative of a relationship between condition information and radio wave information indicative of the radio wave state, where the condition information includes at least one of time information indicative of a time when the radio wave state is measured or position information indicative of a position of the audio system.

Radio frequency transmitter capable of selecting output power control range and wireless communication device including the same

A radio frequency (RF) transmitter including a switched-capacitor digital-to-analog converter (SC-DAC) configured to selectively generate a first RF output signal having a first output power control range or a second RF output signal having a second output power control range from input signals received through a plurality of lines may be provided.

TRANSMITTER CIRCUIT, RECEIVER CIRCUIT, AND COMMUNICATION CIRCUIT
20230268937 · 2023-08-24 · ·

A transmitter circuit coupled to a receiver circuit through wiring. The transmitter circuit transmits, as an input signal, either a first signal of a rectangular waveform having a logic level that changes according to first data, or a second signal having a slope that changes corresponding to second data. The receiver circuit includes an analog-to-digital (AD) converter receiving the input signal through the wiring, and a processing circuit configured to process an output of the AD converter, to thereby determine whether the input signal is the first signal or the second signal, and upon determining that the input signal is the first signal or a second signal, acquire the first data or the second data based on the logic level of the first signal or the slope of the second signal, as the case may be.

Interface between radio receiver and baseband receiver and a method for converting RF-signals to BB-signals
11329678 · 2022-05-10 · ·

A receiver system includes an interface between a radio receiver on a radio frequency (RF)-side and a baseband receiver on a baseband (BB)-side. The receiver includes an antenna for receiving radio frequency signals and an analogue-to-digital converter for converting received analogue signals to digital signals. The digital signals are further processed in the baseband receiver by a digital signal processing unit. The analogue-to-digital converter is a sigma-delta converter, which includes a sigma-delta modulator on the RF-side and a decimation filter on the BB-side. The sigma-delta modulator and the decimation filter are connected only by single-bit in-phase (I) and quadrature (Q) streams output lines.

Integrated mixed-signal ASIC with ADC, DAC, and DSP

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.

2G/3G Signals Over 4G/5G Virtual RAN Architecture
20220141072 · 2022-05-05 ·

Systems, methods and computer software are disclosed for providing 2G/3G communication over 4G/5G distributed unit (DU) in a virtual Radio Access Network (RAN) architecture.